Re: Fix some MIPS operand typos

[Richard Sandiford <rdsandiford at googlemail dot com>]

"Maciej W. Rozycki" <macro@codesourcery.com> writes:
> 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
>
> 	include/opcode/
> 	* mips.h: Refer to general and coprocessor registers in 
> 	coprocessor instruction field documentation.
>
>   Maciej
>
> binutils-mips-include-ops-doc.diff
> Index: binutils-fsf-trunk-quilt/include/opcode/mips.h
> ===================================================================
> --- binutils-fsf-trunk-quilt.orig/include/opcode/mips.h	2013-06-25 01:09:04.000000000 +0100
> +++ binutils-fsf-trunk-quilt/include/opcode/mips.h	2013-06-25 23:50:55.211225703 +0100
> @@ -441,14 +441,14 @@ struct mips_opcode
>     "W" 5 bit same register used as floating target and destination (OP_*_FT)
>  
>     Coprocessor instructions:
> -   "E" 5 bit target register (OP_*_RT)
> -   "G" 5 bit destination register (OP_*_RD)
> +   "E" 5 bit general register (OP_*_RT)
> +   "G" 5 bit coprocessor register (OP_*_RD)

"E" is a coprocessor register, not a general register.

The current "E" seems fine to me.  It's consistent with "t", etc.,
and we have RD_t for a reason.

In case this response tempts you to try a wholesale edit of the format
comments: please hold off for now.  The reason I noticed in the first
place is that I'm working on a series to change the way we handle this
stuff, and that series might well und up changing these comments anyway.
I just wanted to fix wrong info as I found it.

I applied the patch below, which includes another mismatch I found later.

Thanks,
Richard


include/opcode/
	* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
	Use "source" rather than "destination" for microMIPS "G".

gas/
	* config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.

Index: include/opcode/mips.h
===================================================================
--- include/opcode/mips.h	2013-06-26 07:58:47.721400400 +0100
+++ include/opcode/mips.h	2013-06-26 07:59:01.751513887 +0100
@@ -377,7 +377,7 @@ struct mips_opcode
 
    Each of these characters corresponds to a mask field defined above.
 
-   "1" 5 bit sync type (OP_*_SHAMT)
+   "1" 5 bit sync type (OP_*_STYPE)
    "<" 5 bit shift amount (OP_*_SHAMT)
    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
    "a" 26 bit target address (OP_*_TARGET)
@@ -1742,7 +1742,7 @@ #define MICROMIPSOP_MASK_EVAOFFSET	0x1ff
    others too).
 
    "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
-   "1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
+   "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
    "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
    ">" shift amount between 32 and 63, stored after subtracting 32
        (MICROMIPSOP_*_SHAMT)
@@ -1814,9 +1814,9 @@ #define MICROMIPSOP_MASK_EVAOFFSET	0x1ff
 
    Coprocessor instructions:
    "E" 5-bit target register (MICROMIPSOP_*_RT)
-   "G" 5-bit destination register (MICROMIPSOP_*_RS)
+   "G" 5-bit source register (MICROMIPSOP_*_RS)
    "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
-   "+D" combined destination register ("G") and sel ("H") for CP0 ops,
+   "+D" combined source register ("G") and sel ("H") for CP0 ops,
 	for pretty-printing in disassembly only
 
    Macro instructions:
Index: gas/config/tc-mips.c
===================================================================
--- gas/config/tc-mips.c	2013-06-26 07:58:47.721400400 +0100
+++ gas/config/tc-mips.c	2013-06-26 07:59:16.859636083 +0100
@@ -10975,7 +10975,7 @@ #define USE_BITS(mask,shift)	(used_bits
       case '%': USE_BITS (OP_MASK_VECALIGN,	OP_SH_VECALIGN); break;
       case '[': break;
       case ']': break;
-      case '1':	USE_BITS (OP_MASK_SHAMT,	OP_SH_SHAMT);	break;
+      case '1': USE_BITS (OP_MASK_STYPE,	OP_SH_STYPE);	break;
       case '2': USE_BITS (OP_MASK_BP,		OP_SH_BP);	break;
       case '3': USE_BITS (OP_MASK_SA3,  	OP_SH_SA3);	break;
       case '4': USE_BITS (OP_MASK_SA4,  	OP_SH_SA4);	break;