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Re: question about cache miss
- From: William Cohen <wcohen at redhat dot com>
- To: tgh <tianguanhua at ncic dot ac dot cn>
- Cc: systemtap at sourceware dot org
- Date: Mon, 06 Jul 2009 15:16:24 -0400
- Subject: Re: question about cache miss
- References: <24227355.post@talk.nabble.com> <DCF175E9-22B3-43E3-B4F2-35159B956ED9@physik.rwth-aachen.de> <24230120.post@talk.nabble.com> <1246138142.2583.154.camel@hermans.wildebeest.org> <068101c9f85f$534d3480$f9e79d80$@ac.cn> <1246255430.8053.1.camel@hermans.wildebeest.org> <06d201c9f8ad$8e16a850$aa43f8f0$@ac.cn> <09ac01c9fad8$a4a22720$ede67560$@ac.cn>
tgh wrote:
> Hi
> Does systemtap support cache miss instrumentation ? how to get it
>
> thanks
>
You mean the processor's L1/L2/L3 cache? SystemTap doesn't have access to the
performance monitoring hardware on the processors. You might look at the
Performance Counters for Linux (PCL) which has been pulled into the 2.6.31 kernel:
http://lwn.net/Articles/324775/
http://www.h-online.com/open/Kernel-Log-Main-development-phase-of-Linux-2-6-31-completed--/news/113614
The current PCL implementation doesn't have a interface available for the kernel
calls. This makes it a bit difficult for SystemTap to use it.
If you are talking about software caches in the kernel, you might be able to
find the appropriate functions to probe to allow systemtap to observe those
events. Something similar to the the vm.pagefault probe.
-Will