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RE: [ECOS] generating interrupts in ARM-PID (SID simulator)
- From: "Robert Cragie" <rcc at jennic dot com>
- To: "Partha Palit" <chessrook2001 at yahoo dot com>
- Cc: "ECOS" <ecos-discuss at sources dot redhat dot com>, "SID" <sid at sources dot redhat dot com>
- Date: Wed, 2 Jul 2003 11:10:31 +0100
- Subject: RE: [ECOS] generating interrupts in ARM-PID (SID simulator)
> As recommened by Robert, I tried using the interrupt
> 11.It seemed to work, but it showed up as spurious
> interrupt which is not handled by the ARM Hal. I guess
> this is becuase ARM recognizes level triggered
> interrupts as pointed out by Robert.
A spurious interrupt is simply one which is not handled by the software
interrupt handling mechanism. It is nothing to do with level or
edge-triggered interrupts. All processors essentially work on
level-triggered interrupts. An edge-triggered interrupt is where an edge is
simply latched to assert a level, and then cleared in a defined way to
negate a level, usually by writing to some register.
So if you are getting a spurious interrupt, you are at least seeing the
interrupt, which is progress. Put a breakpoint on hal_IRQ_handler and see
what it's doing. I would guess you are not installing the interrupt handler
properly or the numbers are not corresponding or something - did you try the
sample source code I included?
You could also look at the Interrupt Controller registers on the PID
simulator to give you a clue as to what's going on, e.g. reading IRQStatus
will tell you active interrupts (i.e. where there is an interrupt and it is
also enabled) and reading IRQRawStatus will tell you actual interrupts (i.e.
where there is an interrupt even if it is disabled) (note I am assuming the
SID model matches this exactly):
Address Read Write
0x0A000000 IRQStatus Reserved
0x0A000004 IRQRawStatus Reserved
0x0A000008 IRQEnable IRQEnableSet
0x0A00000C Reserved IRQEnableClear
0x0A000010 Reserved IRQSoft(Programmed IRQ Interrupt)
0x0A000100 FIQStatus Reserved
0x0A000104 FIQRawStatus Reserved
0x0A000108 FIQEnable FIQEnableSet
0x0A00010C Reserved FIQEnableClear
0x0A000110 Reserved Reserved
0x0A000114 FIQSource FIQSource
Note that these will normally be manipulated by the HAL when interrupts are
enabled/disabled/handled etc. and should not be tampered with unless you are
specifically trying to debug something.
> -->Q: Could anyone kindly tell how to generate pulses
> of definite time period using sid-sched? I guess a
> timer can be used, but in the SID configuration file I
> see that the timers have inputs from the cpu itself.
> Is there anything simpler?
Over to Frank and the SID guys, where you seem to have got a comprehensive
Robert Cragie, Design Engineer
Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
http://www.jennic.com Tel: +44 (0) 114 281 2655