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RE: Trying to run on pid7t board
- From: "Robert Cragie" <rcc at jennic dot com>
- To: "Frank Ch. Eigler" <fche at redhat dot com>
- Cc: <sid at sources dot redhat dot com>
- Date: Wed, 21 Aug 2002 19:15:24 +0100
- Subject: RE: Trying to run on pid7t board
> On Wed, Aug 21, 2002 at 05:24:50PM +0100, Robert Cragie wrote:
> > [...]
> > I then connect to it using gdb (insight 5.0), and connect
> successfully to
> > the target. I then download the test, and inspect memory at 0x8000, no
> > problem, it's there. However, when I start to run, it hits the
> breakpoint I
> > have set, but I notice all the code has vanished at 0x8000, and it's
> > executing 0x00000000 each time. Any idea what's going on?
>
> Yes, that is odd. Can you tell me why you think it's executing 0x0?
> You could show gdb's side of the conversation, either a console script,
> or maybe even include packet traces as per `(gdb) set remote debug 3'.
If I specify --trace-semantics in the sid command line I get the following:
0x8040: LDR_PRE_INC_IMM_OFFSET gr[0]:=0x8048
0x8044: MOV_REG_IMM_SHIFT pc:=0x8048
0x8048: LDR_PRE_INC_IMM_OFFSET gr[0]:=0xb000020
0x804c: STR_PRE_INC_IMM_OFFSET memory[0xb000020]:=0xb000020
0x8050: AND_REG_IMM_SHIFT
0x8054: AND_REG_IMM_SHIFT
0x8058: AND_REG_IMM_SHIFT
0x805c: AND_REG_IMM_SHIFT
...AND_REG_IMM_SHIFT looks like andeq r0,r0,r0 to me (i.e. NOP). I stepped
through the code and sure enough what happens is that indeed the first three
opcodes run OK, but when the fourth opcode is run, it screws up thereafter -
all the memory gets set to 0.
On the PID board, 'str r0,[r0]', where r0 is 0xb000020, changes the mapping
of the PID board mapping RAM to 0x0000000 instead of ROM - if the REMAP
board link (LK18) is in place. So it looks like the simulation of this is
doing something odd causing it to go wrong - I would expect it to just carry
on, as I would guess the software component of the simulation would have
already remapped (as a debug monitor on a real board would have), and once
this is done, it's done until the next reset.
Robert Cragie, Design Engineer
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