best options for a wide bus?

[Paul Miach <paul dot miach at edion dot com>]

Hi,

I am looking at getting SID to simulate a bus architecture with busses
wider than 32 bits, ideally busses that are a little over 64 bits wide
(256 bit would be nice, but I can hide this within components).  From
looking at the code and the demos (should be demo?) I seem to have three
options;

- Use multiple 32 bit busses to reach the required width
- Use "memory" as a pseudo bus
- Extend the bus object/component to cope with more than 32 bits.

In terms of performance (simulator time) and ease of implementation,
what are the trade off in each of the above?

Cheers.

--
Paul Miach