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Re: [PATCH] Optimize MIPS memcpy
- From: Andrew Pinski <pinskia at gmail dot com>
- To: Steve Ellcey <sellcey at mips dot com>
- Cc: Maxim Kuvyrkov <maxim at codesourcery dot com>, "Joseph S. Myers" <joseph at codesourcery dot com>, libc-ports at sourceware dot org
- Date: Mon, 15 Oct 2012 13:20:41 -0700
- Subject: Re: [PATCH] Optimize MIPS memcpy
- References: <5044746c.23eb440a.75e2.618f@mx.google.com> <1346771341.14333.20.camel@ubuntu-sellcey> <596797ED-6575-456D-98FD-C13A209DBC49@mentor.com> <1346948701.14333.152.camel@ubuntu-sellcey> <F265181B-6B5C-401B-B7CC-DC206B601795@codesourcery.com> <1347376645.14333.319.camel@ubuntu-sellcey> <F0856A02-839F-45C7-BF93-AA59E030A015@codesourcery.com> <1348166309.6170.55.camel@ubuntu-sellcey> <25105334-8813-4532-AC0E-B3A44BE69A19@codesourcery.com> <5B30D440-A918-4352-8DED-A7D681DF0338@codesourcery.com> <1349715796.30194.131.camel@ubuntu-sellcey> <954E9625-0D5C-4295-9229-C16A3F5C200D@codesourcery.com> <1350323373.2044.7.camel@ubuntu-sellcey>
On Mon, Oct 15, 2012 at 10:49 AM, Steve Ellcey <sellcey@mips.com> wrote:
> On Tue, 2012-10-09 at 11:30 +1300, Maxim Kuvyrkov wrote:
>
>> I too want to keep prepare-for-store prefetches is possible. For debugging purposes you could amend
>> prepare-for-store prefetch macros to trigger a loop that would unconditionally clobber memory locations
>> that prepare-for-store is expected to zero-out. Or add some other assertions to help out with debugging.
>>
>> Thanks,
>>
>> --
>> Maxim Kuvyrkov
>> CodeSourcery / Mentor Graphics
>
> Maxim,
>
> Could you try running this test program on your system. I want to see
> if it verifies that your machine is doing 32 byte prefetches. The
> output I get looks like:
>
>
> 0x004754a0, (0x004754a0 to 0x004754c0, 32 byte prefetch)
> 0x004754a1, (0x004754a0 to 0x004754c0, 32 byte prefetch)
> 0x004754a2, (0x004754a0 to 0x004754c0, 32 byte prefetch)
> 0x004754a3, (0x004754a0 to 0x004754c0, 32 byte prefetch)
> 0x004754a4, (0x004754a0 to 0x004754c0, 32 byte prefetch)
> 0x004754a5, (0x004754a0 to 0x004754c0, 32 byte prefetch)
> .
> .
> .
> 0x0047589b, (0x00475880 to 0x004758a0, 32 byte prefetch)
> 0x0047589c, (0x00475880 to 0x004758a0, 32 byte prefetch)
> 0x0047589d, (0x00475880 to 0x004758a0, 32 byte prefetch)
> 0x0047589e, (0x00475880 to 0x004758a0, 32 byte prefetch)
> 0x0047589f, (0x00475880 to 0x004758a0, 32 byte prefetch)
On:
system type : EBB6300 (CN6335p2.1-1500-AAP)
processor : 0
cpu model : Cavium Octeon II V0.9
BogoMIPS : 3000.00
wait instruction : yes
microsecond timers : yes
tlb_entries : 128
extra interrupt vector : yes
hardware watchpoint : yes, count: 2, address/irw mask: [0x0ffc, 0x0ffb]
ASEs implemented :
shadow register sets : 1
kscratch registers : 3
core : 0
VCED exceptions : not available
VCEI exceptions : not available
I get:
...
0x200757cb, (no zeros)
0x200757cc, (no zeros)
0x200757cd, (no zeros)
0x200757ce, (no zeros)
0x200757cf, (0x20075780 to 0x20075800, 128 byte prefetch)
.....
0x2007587a, (no zeros)
0x2007587b, (no zeros)
0x2007587c, (no zeros)
0x2007587d, (no zeros)
0x2007587e, (no zeros)
0x2007587f, (no zeros)
0x20075880, (0x20075880 to 0x20075900, 128 byte prefetch)
Thanks,
Andrew Pinski
>
> Steve Ellcey
> sellcey@mips.com