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Re: [PATCH 1/3, MIPS] Rewrite MIPS' atomic.h to use __atomic_* builtins.


On 14/06/2012, at 11:06 PM, Joseph S. Myers wrote:

> On Thu, 14 Jun 2012, Maxim Kuvyrkov wrote:
> 
>> This patch rewrites MIPS' atomic.h to use __atomic_* builtins instead of 
>> inline assembly.  These builtins are available in recent version of GCC 
>> and correspond to C++11 memory model support, they also map very well to 
>> GLIBC's atomic_* macros.
> 
> They are available in GCC 4.7 and later (with your patches being for 4.8 
> and later), but the documented minimum GCC version for building glibc is 
> 4.3, and at least 4.4 and later should actually work.
> 
> Thus, these new definitions should be conditional on __GNUC_PREREQ (4, 8), 
> with the old definitions remaining when glibc is built with older GCC, 
> until in a few years' time 4.8 or later is the minimum version for 
> building glibc and the conditionals can be removed.
> 
>> 	* sysdeps/mips/bit/atomic.h: Rewrite using __atomic_* builtins.
> 
> "bits", and glibc follows the GNU Coding Standards for conditional 
> changes, so I think you want something like
> 
> 	[__GNUC_PREREQ (4, 8)] (__arch_foo): Define in terms of 
> 	__atomic_bar.
> 
> repeated for each macro changed.

OK.  Updated patch attached.

Any further comments?

Thank you,

--
Maxim Kuvyrkov
CodeSourcery / Mentor Graphics


[PATCH 1/3] Rewrite MIPS' atomic.h to use __atomic_* builtins.

2012-06-14  Tom de Vries  <vries@codesourcery.com>
	    Maxim Kuvyrkov  <maxim@codesourcery.com>

	* sysdeps/mips/bit/atomic.h [__GNUC_PREREQ (4, 8)]
	(__arch_compare_and_exchange_bool_acq_32_int,)
	(__arch_compare_and_exchange_bool_rel_32_int,)
	(__arch_compare_and_exchange_val_acq_32_int,)
	(__arch_compare_and_exchange_val_rel_32_int,)
	(__arch_compare_and_exchange_bool_acq_64_int,)
	(__arch_compare_and_exchange_bool_rel_64_int,)
	(__arch_compare_and_exchange_val_acq_64_int,)
	(__arch_compare_and_exchange_val_rel_64_int):
	Define in terms of __atomic_compare_exchange_n.
	[__GNUC_PREREQ (4, 8)]
	(__arch_exchange_acq_32_int, __arch_exchange_rel_32_int,)
	(__arch_exchange_acq_64_int, __arch_exchange_rel_64_int):
	Define in terms of __atomic_exchange_n.
	[__GNUC_PREREQ (4, 8)]
	(__arch_fetch_and_add_32_int, __arch_fetch_and_add_64_int):
	Define in terms of __atomic_fetch_add.
---
 sysdeps/mips/bits/atomic.h |  179 +++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 178 insertions(+), 1 deletions(-)

diff --git a/sysdeps/mips/bits/atomic.h b/sysdeps/mips/bits/atomic.h
index 4d51d7f..7150e43 100644
--- a/sysdeps/mips/bits/atomic.h
+++ b/sysdeps/mips/bits/atomic.h
@@ -1,5 +1,5 @@
 /* Low-level functions for atomic operations. Mips version.
-   Copyright (C) 2005 Free Software Foundation, Inc.
+   Copyright (C) 2005-2012 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -78,6 +78,182 @@ typedef uintmax_t uatomic_max_t;
 #define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X)
 #define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC)
 
+#if __GNUC_PREREQ (4, 8)
+/* The __atomic_* builtins are available in GCC 4.7 and later, but MIPS
+   support for their efficient implementation was added only in GCC 4.8.  */
+
+/* Compare and exchange.
+   For all "bool" routines, we return FALSE if exchange succesful.  */
+
+#define __arch_compare_and_exchange_bool_acq_8_int(mem, newval, oldval) \
+  (abort (), 0)
+
+#define __arch_compare_and_exchange_bool_rel_8_int(mem, newval, oldval) \
+  (abort (), 0)
+
+#define __arch_compare_and_exchange_bool_acq_16_int(mem, newval, oldval) \
+  (abort (), 0)
+
+#define __arch_compare_and_exchange_bool_rel_16_int(mem, newval, oldval) \
+  (abort (), 0)
+
+#define __arch_compare_and_exchange_bool_acq_32_int(mem, newval, oldval) \
+  ({									\
+    typeof (*mem) __oldval = (oldval);					\
+    !__atomic_compare_exchange_n (mem, &__oldval, newval, 0,		\
+				  __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);	\
+  })
+
+#define __arch_compare_and_exchange_bool_rel_32_int(mem, newval, oldval) \
+  ({									\
+    typeof (*mem) __oldval = (oldval);					\
+    !__atomic_compare_exchange_n (mem, &__oldval, newval, 0,		\
+				  __ATOMIC_RELEASE, __ATOMIC_RELAXED);	\
+  })
+
+#define __arch_compare_and_exchange_val_acq_8_int(mem, newval, oldval) \
+  (abort (), 0)
+
+#define __arch_compare_and_exchange_val_rel_8_int(mem, newval, oldval) \
+  (abort (), 0)
+
+#define __arch_compare_and_exchange_val_acq_16_int(mem, newval, oldval) \
+  (abort (), 0)
+
+#define __arch_compare_and_exchange_val_rel_16_int(mem, newval, oldval) \
+  (abort (), 0)
+
+#define __arch_compare_and_exchange_val_acq_32_int(mem, newval, oldval) \
+  ({									\
+    typeof (*mem) __oldval = (oldval);					\
+    __atomic_compare_exchange_n (mem, &__oldval, newval, 0,		\
+				 __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);	\
+    __oldval;								\
+  })
+
+#define __arch_compare_and_exchange_val_rel_32_int(mem, newval, oldval) \
+  ({									\
+    typeof (*mem) __oldval = (oldval);					\
+    __atomic_compare_exchange_n (mem, &__oldval, newval, 0,		\
+				 __ATOMIC_RELEASE, __ATOMIC_RELAXED);	\
+    __oldval;								\
+  })
+
+#if _MIPS_SIM == _ABIO32
+  /* We can't do an atomic 64-bit operation in O32.  */
+# define __arch_compare_and_exchange_bool_acq_64_int(mem, newval, oldval) \
+  (abort (), 0)
+# define __arch_compare_and_exchange_bool_rel_64_int(mem, newval, oldval) \
+  (abort (), 0)
+# define __arch_compare_and_exchange_val_acq_64_int(mem, newval, oldval) \
+  (abort (), 0)
+# define __arch_compare_and_exchange_val_rel_64_int(mem, newval, oldval) \
+  (abort (), 0)
+#else
+# define __arch_compare_and_exchange_bool_acq_64_int(mem, newval, oldval) \
+  __arch_compare_and_exchange_bool_acq_32_int (mem, newval, oldval)
+
+# define __arch_compare_and_exchange_bool_rel_64_int(mem, newval, oldval) \
+  __arch_compare_and_exchange_bool_rel_32_int (mem, newval, oldval)
+
+# define __arch_compare_and_exchange_val_acq_64_int(mem, newval, oldval) \
+  __arch_compare_and_exchange_val_acq_32_int (mem, newval, oldval)
+
+# define __arch_compare_and_exchange_val_rel_64_int(mem, newval, oldval) \
+  __arch_compare_and_exchange_val_rel_32_int (mem, newval, oldval)
+
+#endif
+
+/* Compare and exchange with "acquire" semantics, ie barrier after.  */
+
+#define atomic_compare_and_exchange_bool_acq(mem, new, old)             \
+  (__atomic_bool_bysize (__arch_compare_and_exchange_bool_acq, int,	\
+			 mem, new, old))
+
+#define atomic_compare_and_exchange_val_acq(mem, new, old)              \
+  __atomic_val_bysize (__arch_compare_and_exchange_val_acq, int,	\
+		       mem, new, old)
+
+/* Compare and exchange with "release" semantics, ie barrier before.  */
+
+#define atomic_compare_and_exchange_bool_rel(mem, new, old)		\
+  (__atomic_bool_bysize (__arch_compare_and_exchange_bool_rel, int,	\
+			 mem, new, old))
+
+#define atomic_compare_and_exchange_val_rel(mem, new, old)	    \
+  __atomic_val_bysize (__arch_compare_and_exchange_val_rel, int,    \
+                       mem, new, old)
+
+
+/* Atomic exchange (without compare).  */
+
+#define __arch_exchange_acq_8_int(mem, newval) \
+  (abort (), 0)
+
+#define __arch_exchange_rel_8_int(mem, newval) \
+  (abort (), 0)
+
+#define __arch_exchange_acq_16_int(mem, newval) \
+  (abort (), 0)
+
+#define __arch_exchange_rel_16_int(mem, newval) \
+  (abort (), 0)
+
+#define __arch_exchange_acq_32_int(mem, newval) \
+  __atomic_exchange_n (mem, newval, __ATOMIC_ACQUIRE)
+
+#define __arch_exchange_rel_32_int(mem, newval) \
+  __atomic_exchange_n (mem, newval, __ATOMIC_RELEASE)
+
+#if _MIPS_SIM == _ABIO32
+/* We can't do an atomic 64-bit operation in O32.  */
+# define __arch_exchange_acq_64_int(mem, newval) \
+  (abort (), 0)
+# define __arch_exchange_rel_64_int(mem, newval) \
+  (abort (), 0)
+#else
+# define __arch_exchange_acq_64_int(mem, newval) \
+  __atomic_exchange_n (mem, newval, __ATOMIC_ACQUIRE)
+
+# define __arch_exchange_rel_64_int(mem, newval) \
+  __atomic_exchange_n (mem, newval, __ATOMIC_RELEASE)
+#endif
+
+#define atomic_exchange_acq(mem, value) \
+  __atomic_val_bysize (__arch_exchange_acq, int, mem, value)
+
+#define atomic_exchange_rel(mem, value) \
+  __atomic_val_bysize (__arch_exchange_rel, int, mem, value)
+
+
+/* Atomically add value and return the previous (unincremented) value.  */
+
+#define __arch_exchange_and_add_8_int(mem, newval) \
+  (abort (), (typeof(*mem)) 0)
+
+#define __arch_exchange_and_add_16_int(mem, newval) \
+  (abort (), (typeof(*mem)) 0)
+
+#define __arch_exchange_and_add_32_int(mem, value) \
+  __atomic_fetch_add (mem, value, __ATOMIC_ACQ_REL)
+
+#if _MIPS_SIM == _ABIO32
+/* We can't do an atomic 64-bit operation in O32.  */
+# define __arch_exchange_and_add_64_int(mem, value) \
+  (abort (), (typeof(*mem)) 0)
+#else
+# define __arch_exchange_and_add_64_int(mem, value) \
+  __atomic_fetch_add (mem, value, __ATOMIC_ACQ_REL)
+#endif
+
+/* ??? Barrier semantics for atomic_exchange_and_add appear to be
+   undefined.  Use full barrier for now, as that's safe.  */
+#define atomic_exchange_and_add(mem, value) \
+  __atomic_val_bysize (__arch_exchange_and_add, int, mem, value)
+#else /* !__GNUC_PREREQ (4, 8) */
+/* This implementation using inline assembly will be removed once GLIBC
+   requires GCC 4.8 or later to build.  */
+
 /* Compare and exchange.  For all of the "xxx" routines, we expect a
    "__prev" and a "__cmp" variable to be provided by the enclosing scope,
    in which values are returned.  */
@@ -315,6 +491,7 @@ typedef uintmax_t uatomic_max_t;
 #define atomic_exchange_and_add(mem, value) \
   __atomic_val_bysize (__arch_exchange_and_add, int, mem, value,	      \
 		       MIPS_SYNC_STR, MIPS_SYNC_STR)
+#endif /* __GNUC_PREREQ (4, 8) */
 
 /* TODO: More atomic operations could be implemented efficiently; only the
    basic requirements are done.  */
-- 
1.7.4.1



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