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Memory barrier for MIPS test_and_set
- From: Daniel Jacobowitz <drow at false dot org>
- To: libc-ports at sourceware dot org
- Date: Fri, 28 Mar 2008 13:43:05 -0400
- Subject: Memory barrier for MIPS test_and_set
I've committed this patch from Robin Randhawa at MIPS, which adds a
missing sync. I see that the kernel now emulates sync, so we can do
this with impunity...
--
Daniel Jacobowitz
CodeSourcery
2008-03-27 Robin Randhawa <robin@mips.com>
* sysdeps/unix/sysv/linux/mips/sys/tas.h: Added memory barriers to
enforce strict ordering on weakly ordered systems.
Index: sysdeps/unix/sysv/linux/mips/sys/tas.h
===================================================================
--- sysdeps/unix/sysv/linux/mips/sys/tas.h (revision 197772)
+++ sysdeps/unix/sysv/linux/mips/sys/tas.h (working copy)
@@ -40,17 +40,19 @@ __NTH (_test_and_set (int *p, int v))
__asm__ __volatile__
("/* Inline test and set */\n"
- "1:\n\t"
".set push\n\t"
#if _MIPS_SIM == _ABIO32
".set mips2\n\t"
#endif
+ "sync\n\t"
+ "1:\n\t"
"ll %0,%3\n\t"
"move %1,%4\n\t"
"beq %0,%4,2f\n\t"
"sc %1,%2\n\t"
- ".set pop\n\t"
"beqz %1,1b\n"
+ "sync\n\t"
+ ".set pop\n\t"
"2:\n\t"
"/* End test and set */"
: "=&r" (r), "=&r" (t), "=m" (*p)