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Re: [PATCH 2/2] PPC64: Add libmvec SIMD double-precision power function.
- From: Florian Weimer <fweimer at redhat dot com>
- To: Shawn Landden <shawn at git dot icu>
- Cc: libc-alpha at sourceware dot org, Tulio Magno Quites Machado Filho <tuliom at ascii dot art dot br>, Joseph Myers <joseph at codesourcery dot com>
- Date: Tue, 25 Jun 2019 20:01:26 +0200
- Subject: Re: [PATCH 2/2] PPC64: Add libmvec SIMD double-precision power function.
- References: <20190625175302.26676-1-shawn@git.icu> <20190625175302.26676-2-shawn@git.icu>
* Shawn Landden:
> Based off the ./sysdeps/ieee754/dbl-64/pow.c implementation,
> and provides identical results.
>
> However two of those *identical* results results in 1 ulp test failures,
> so I'm not sure how the non-SIMD versions are passing. These clearly should allow
> the 1 ulp variation (and the float128 results are right in the middle), and
> this is allowed by the standard:
> Maximal error of `pow_vlen2'
> is : 1 ulp
> accepted: 0 ulp
I suspect this is because the scalar version looks for exceptions under
the name “pow”, and you haven't added an exception for “pow_vlen2” in
this patch.
Thanks,
Florian