Re: [patches] Re: [PATCH v4 16/17] RISC-V: Build Infastructure

[Palmer Dabbelt <palmer at dabbelt dot com>]

On Mon, 15 Jan 2018 09:44:44 PST (-0800), joseph@codesourcery.com wrote:
> On Sat, 13 Jan 2018, Palmer Dabbelt wrote:
>
> > diff --git a/sysdeps/riscv/preconfigure b/sysdeps/riscv/preconfigure
>
> > +    case "$flen" in
> > +    64)
> > +    	float_machine=rvd
> > +	with_fp_cond=1
> > +    	;;
> > +    "")
> > +    	float_machine=
> > +	with_fp_cond=0
> > +    	;;
> > +    *)
> > +    	echo "Unable to determine FLEN" >&2
> > +    	exit 1
> > +    	;;
> > +    esac
>
> It's deliberate that you don't support the "f" ABI.  Is it also deliberate
> that here you don't support the case of "f" hardware (float but not double
> supported in hardware) with the soft-float ABI, despite having sysdeps
> directories structured to distinguish rvf and rvd?

Yes: the idea here was to reduce the amount of targets that the RISC-V port 
needed to support right now.  We originally supported all these targets in 
glibc so the code is still organized that way.  I'd prefer to leave the 
organization as it is in case we want to add support for the F ISAs and ABIs, 
as I have a feeling we might want to extend this in the future.