Re: [patches] Re: [PATCH v4 08/17] RISC-V: Generic <math.h> and soft-fp Routines

[Palmer Dabbelt <palmer at dabbelt dot com>]

On Mon, 15 Jan 2018 08:59:06 PST (-0800), joseph@codesourcery.com wrote:
> On Sat, 13 Jan 2018, Palmer Dabbelt wrote:
>
> > This patch contains the miscellaneous math routines and headers we have
> > implemented for RISC-V.  This includes things from <math.h> that aren't
> > completely ISA-generic, floating-point bit manipulation, and soft-fp
> > hooks.
> >
> > FIXME: add ieee745/soft-fp via a riscv/soft-fp directory.
>
> Again, it should be a riscv/nofpu directory, and riscv/soft-fp shouldn't
> exist.

Ya, sorry about that, this should be fixed.

> > diff --git a/sysdeps/riscv/math-tests.h b/sysdeps/riscv/math-tests.h
>
> > +#define EXCEPTION_TESTS_float 0
> > +#define EXCEPTION_TESTS_double        0
> > +#define EXCEPTION_TESTS_long_double   0
>
> I'd expect that to be conditional on soft-float, as exceptions should be
> supported for hard-float (whether the hard-float or soft-float ABI is
> used).  I'd also expect ROUNDING_TESTS_* to be defined to ((MODE) ==
> FE_TONEAREST) for soft-float, as on other architectures, given that
> rounding modes are only supported for hard-float.

The RISC-V ISA doesn't support taking traps on floating-point exceptions, just 
polling the flags register.  My understanding was that we should be 
unconditionally setting these flags, but if I'm wrong we'll go through and 
change it.