This is the mail archive of the libc-alpha@sourceware.org mailing list for the glibc project.

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]

Re: [PATCH 1/3] Guess L1 cache linesize for aarch64

From: Andrew Pinski <pinskia at gmail dot com>
To: Siddhesh Poyarekar <siddhesh at gotplt dot org>
Cc: Richard Henderson <rth at twiddle dot net>, GNU C Library <libc-alpha at sourceware dot org>, Marcus Shawcroft <marcus dot shawcroft at arm dot com>
Date: Thu, 8 Jun 2017 22:52:51 -0700
Subject: Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
Authentication-results: sourceware.org; auth=none
References: <20170608225728.26779-1-rth@twiddle.net> <20170608225728.26779-2-rth@twiddle.net> <a86d5187-7536-fca0-ac61-259cb3d873e3@gotplt.org>

On Thu, Jun 8, 2017 at 10:51 PM, Siddhesh Poyarekar <siddhesh@gotplt.org> wrote:
> On Friday 09 June 2017 04:27 AM, Richard Henderson wrote:
>> Using the cache hierarchy linesize minimum in CTR_EL0.
>> See the comment within the code for rationale.
>>
>>       * sysdeps/unix/sysv/linux/aarch64/sysconf.c: New file.
>>
>
> Looks good to me.

And me too.

Thanks,
ANdrew

>
> Thanks,
> Siddhesh

References:
- [PATCH 0/3] Add some missing cache infomation
  - From: Richard Henderson
- [PATCH 1/3] Guess L1 cache linesize for aarch64
  - From: Richard Henderson
- Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
  - From: Siddhesh Poyarekar

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]