This is the mail archive of the libc-alpha@sourceware.org mailing list for the glibc project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [RFC PATCH 00/29] arm64: Scalable Vector Extension core support


On 12/01/2016 11:30 AM, Dave Martin wrote:

The VL value is implicitly thread-local data, and the encoded state may have
an implicit dependency on it, although it does not contain vector registers
as such.

This doesn't sound like an absolute requirement to me.

If we presume that the SVE registers never need to get saved or
restored, what stops the context data format being VL-independent?

I'm concerned the suspended computation has code which has been selected to fit a particular VL value.

> If the save/restore logic doesn't touch SVE, which would its
> implementation be VL-dependent?

Because it has been optimized for a certain vector length?

Because the SVE procedure call standard determines that the SVE
registers are caller-save,

By the way, how is this implemented?  Some of them overlap existing
callee-saved registers.

Basically, all the *new* state is caller-save.

The Neon/FPSIMD regs V8-V15 are callee-save, so in the SVE view
Zn[bits 127:0] is callee-save for all n = 8..15.

Are the extension parts of registers v8 to v15 used for argument passing?

If not, we should be able to use the existing dynamic linker trampoline.

Thanks,
Florian


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]