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[PATCH] [x86_32] Don't use SSE4_2 instructions on Intel Silvermont Micro Architecture.


Same patch as recently committed but for 32 bit.
Attached performance results for current bench glibc test suite.
Hopefully I caught a moment before the freeze of 2.18.

2013-06-30  Liubov Dmitrieva  <liubov.dmitrieva@intel.com>

  * sysdeps/i386/i686/multiarch/memcmp.S: Skip SSE4_2
  version if bit_Slow_SSE4_2 is set.
  * sysdeps/i386/i686/multiarch/strcmp.S: Likewise.
  * sysdeps/i386/i686/multiarch/strncase.S: Likewise.
  * sysdeps/i386/i686/multiarch/strcasecmp.S: Likewise.
  * sysdeps/i386/i686/multiarch/wmemcmp.S: Likewise.

--
Liubov

Attachment: silvermont2.patch
Description: Binary data

Attachment: benchtests_after32.tar.gz
Description: GNU Zip compressed data

Attachment: benchtests_before32.tar.gz
Description: GNU Zip compressed data


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