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Re: [RFC] Lock elision implementation guidelines
- From: Andi Kleen <andi at firstfloor dot org>
- To: libc-alpha at sourceware dot org
- Date: Wed, 12 Jun 2013 15:21:48 -0700
- Subject: Re: [RFC] Lock elision implementation guidelines
- References: <1360527652 dot 3065 dot 11521 dot camel at triegel dot csb> <1370618459 dot 16968 dot 11300 dot camel at triegel dot csb> <20130610114346 dot GA1384 at linux dot vnet dot ibm dot com> <877gi06yc1 dot fsf at tassilo dot jf dot intel dot com> <20130612074948 dot GA20256 at linux dot vnet dot ibm dot com>
Dominik Vogt <vogt@linux.vnet.ibm.com> writes:
>
> It probably depends on the hardware implementation details of the
> HTM system. The idea of the test program was to "break" a HTM
> that aborts a transaction that writes a memory cell if that cell
> is read afterwards from another transaction or outside a
> transaction.
The test case does not break TSX. It has a near perfect commit
rate in fact.
> This is the case for the zEC12, but I don't know the
> details of TSX very well, and I only have access to a
> z/architecture machine. Is there any document available where I
> can look up the TSX implementation details?
http://www.intel.com/software/tsx
e.g. the IDF presentation and the optimization guide.
-Andi
--
ak@linux.intel.com -- Speaking for myself only