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Re: [PATCH] hp-timing for ppc32/64
- From: Benjamin Herrenschmidt <benh at kernel dot crashing dot org>
- To: Steve Munroe <sjmunroe at us dot ibm dot com>
- Cc: Kumar Gala <kumar dot gala at freescale dot com>, libc-alpha at sources dot redhat dot com
- Date: Tue, 18 Oct 2005 09:05:39 +1000
- Subject: Re: [PATCH] hp-timing for ppc32/64
- References: <OFE4E64E02.21B8AF76-ON8625709D.0079C58A-8625709D.007C347F@us.ibm.com>
> > Note that some CPUs like the 970 can have an externally clocked
> > timebase. Apple uses this feature to make the CPU immune to bus/cpu
> > frequency slewing, they use a 33Mhz clock for that.
> >
> The 970 does not implement a alternate timebase. So for 970 the timebase
> is the highest frequency counter available.
I didn't mean an alternate timebase ... I was saying that the 970 does
implement the main timebase, but use the option of having it clocked
externally instead of as a divider of the bus clock (this is an option
that can be toggled in a HID register iirc, in which cas the TB_EN pin
becomes the timebase input).
> It seems that Apple choose 33MHz to meet the minimum (slowest)CPU-clock /
> 32 timebase. But that was their choice. The IBM hardware seems to be
> holding to the CPU_clock / 8 timebase (including 970 based JS20).
No, I think the 33Mhz is due to an HW upper limit when clocking the
timebase externally. IBM doesn't use external clocking.