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As reported by Arnaud on the glibc-bug list, the changes for SSE are not correct (compare with the x86-64 routines). Ok to commit? Andreas 2003-06-15 Andreas Jaeger <aj@suse.de> * sysdeps/i386/fpu/feenablxcpt.c (feenableexcept): Correct setting of MXCSR. * sysdeps/i386/fpu/fedisblxcpt.c (fedisableexcept): Likewise. * sysdeps/i386/fpu/feholdexcpt.c (feholdexcept): Likewise. Reported by Arnaud Desitter <arnaud.desitter@geography.oxford.ac.uk>. ============================================================ Index: sysdeps/i386/fpu/feenablxcpt.c --- sysdeps/i386/fpu/feenablxcpt.c 29 Apr 2003 07:17:24 -0000 1.5 +++ sysdeps/i386/fpu/feenablxcpt.c 15 Jun 2003 19:39:45 -0000 @@ -46,7 +46,7 @@ feenableexcept (int excepts) /* Get the current control word. */ __asm__ ("ldmxcsr %0" : "=m" (*&xnew_exc)); - xnew_exc &= ~excepts; + xnew_exc &= ~(excepts << 7); __asm__ ("stmxcsr %0" : : "m" (*&xnew_exc)); } ============================================================ Index: sysdeps/i386/fpu/fedisblxcpt.c --- sysdeps/i386/fpu/fedisblxcpt.c 29 Apr 2003 07:17:24 -0000 1.5 +++ sysdeps/i386/fpu/fedisblxcpt.c 15 Jun 2003 19:39:45 -0000 @@ -46,7 +46,7 @@ fedisableexcept (int excepts) /* Get the current control word. */ __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc)); - xnew_exc |= excepts; + xnew_exc |= (excepts << 7); __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc)); } ============================================================ Index: sysdeps/i386/fpu/feholdexcpt.c --- sysdeps/i386/fpu/feholdexcpt.c 29 Apr 2003 07:17:24 -0000 1.5 +++ sysdeps/i386/fpu/feholdexcpt.c 15 Jun 2003 19:39:45 -0000 @@ -44,7 +44,7 @@ feholdexcept (fenv_t *envp) __asm__ ("stmxcsr %0" : "=m" (*&xwork)); /* Set all exceptions to non-stop. */ - work |= 0x1f80; + xwork |= 0x1f80; __asm__ ("ldmxcsr %0" : : "m" (*&xwork)); } -- Andreas Jaeger, SuSE Linux AG, aj@suse.de, http://www.suse.de/~aj GPG fingerprint = 93A3 365E CE47 B889 DF7F FED1 389A 563C C272 A126
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