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RE: is it a bug of /glibc/sysdeps/arm/atomicity.h ?
- From: "Hu, Boris" <boris dot hu at intel dot com>
- To: "'Russell King - ARM Linux'" <linux at arm dot linux dot org dot uk>
- Cc: "'Daniel Jacobowitz'" <drow at mvista dot com>, "'Carlos O'Donell'" <carlos at baldric dot uwo dot ca>, "Linux-Arm (E-mail)" <linux-arm at lists dot arm dot linux dot org dot uk>, "Libc-Alpha (E-mail)" <libc-alpha at sources dot redhat dot com>
- Date: Tue, 18 Feb 2003 10:41:49 +0800
- Subject: RE: is it a bug of /glibc/sysdeps/arm/atomicity.h ?
how about this one? thanks.
T1 T2 T3
@ %4=0 @ %4=0 @ %4=1
@ %3=1 @ %3=1 @ %3=2
ldr %1,[%2]
@ %1=0
mov %0,#0
cmp %1,%4
ldr %1,[%2]
@ %1=0
mov %0,#0
cmp %1,%4
swp %0,%3,[%2]
@ *%2=1, %0=0
cmp %1,%0
mov %0,#1
@ result = 1
ldr %1,[%2]
@ %1=1
mov %0,#0
cmp %1,%4
swp %0,%3,[%2]
@ *%2=1, %0=1
cmp %1,%0
swp %0,%3,[%2]
@ *%2=2, %0=1
cmp %1,%0
mov %0,#1
@ result = 1
swpne %1,%0,[%2]
@ *%2=1, %1=1 // *%2 overwritten ??? from 2 -> 1
bne 0b
ldr %1,[%2]
@ %1=1
mov %0,#0
cmp %1,%4
bne 1f
@ result = 0
boris
> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk]
> Sent: 2003?2?17? 18:29
> To: Hu, Boris
> Cc: Linux-Arm (E-mail); "Libc-Alpha (E-mail)"@arm.linux.org.uk
> Subject: Re: is it a bug of /glibc/sysdeps/arm/atomicity.h ?
>
>
> On Mon, Feb 17, 2003 at 05:25:48PM +0800, Hu, Boris wrote:
> > let us consider the following scenario. Suppose there are
> three thread
> > pathes.
> > Init: *p = 0
> > T1 compare_and_swap(p, 0, 1) ;
> > T2 compare_and_swap(p,0,1);
> > T3 compare_and_swap(p,1,2);
> >
> > T1::
> > static inline int compare_and_swap (volatile long int *p,
> > long int oldval, long int newval)
> > {
> > int result, tmp;
> > __asm__ ("\n"
> > "0:\tldr\t%1,[%2]\n\t"
> > "mov\t%0,#0\n\t"
> > "cmp\t%1,%4\n\t"
> > "bne\t1f\n\t" // if now,
> in T2, *p= 1;
> > "swp\t%0,%3,[%2]\n\t"
> > "cmp\t%1,%0\n\t" // if now,
> in T3 *p = 2
> > "swpne\t%1,%0,[%2]\n\t" // *p = 1 ;
> so the modification
> > of T3 will be overwritten. ???
> > "bne\t0b\n\t"
> > "mov\t%0,#1\n"
> > "1:"
> > : "=&r" (result), "=&r" (tmp)
> > : "r" (p), "r" (newval), "r" (oldval)
> > : "cc", "memory");
> > return result;
> > }
> >
> > any opinion? thanks.
>
> You might like to try writing the code like this (to document the
> instruction order executed by each thread. I've eliminated
> instructions
> not actually executed to make it clearer):
>
> T1 T2 T3
> @ %4=0 @ %4=0 @ %4=1
> @ %3=1 @ %3=1 @ %3=2
>
> ldr %1,[%2]
> @ %1=0
> mov %0,#0
> cmp %1,%4
> ldr %1,[%2]
> @ %1=0
> mov %0,#0
> cmp %1,%4
> swp %0,%3,[%2]
> @ *%2=1, %0=0
> cmp %1,%0
> mov %0,#1
> @ result = 1
> ldr %1,[%2]
> @ %1=1
> mov %0,#0
> cmp %1,%4
> swp %0,%3,[%2]
> @ *%2=1, %0=1
> cmp %1,%0
> swpne %1,%0,[%2]
> @ *%2=1, %1=1
> bne 0b
> ldr %1,[%2]
> @ %1=1
> mov %0,#0
> cmp %1,%4
> bne 1f
> @ result = 0
> swp
> %0,%3,[%2]
> @ *%2=2, %0=1
> cmp %1,%0
> mov %0,#1
> @ result = 1
>
> Can you juggle the above around to produce your failure case?
>