Re: [PATCH] ppc32 dl-machine.c

[Segher Boessenkool <segher at koffie dot nl>]

Geoff Keating wrote:
> > > > It also says (elsewhere) that external cache is one example of such a
> > > > "mechanism", and surprise surprise, on the G4 the L2 needs the sync.
> > >
> > > Can you explain why?
> >
> > Because icbi's are executed out-of-order on the G4, and isync does *not*
> > influence that.  As table 2.51 from the G4 UM says:
> 
> "G4" is not a processor name, it's a name for a group of processors,
> the 74xx series, and they all have their own user manuals.  I looked

The 7450 series is usually called G4+, not G4, afaik.  But I'll use
the 74xx names -- much clearer, yes.

Anyway, I was refering to the 7410 UM.

> at the "MPC7450 RISC Microprocessor Family User's manual", dated
> 12/2001 revision 2, which covers 7441, 7445, 7450, 7451, and 7455.
> Table 2-51 is "Move to/from Condition Register Instructions" and has
> no obvious relevance.  Please be more careful with your references.

It's 2-58 in that manual.

> 
> I did find section 3.3.4.8, which describes icbi.  It does seem to
> indicate that the 7451 needs the second sync:

My revision of the 7450 UM document (rev 0) has this in section 3.4.4.8,
and refers to the 7450 (of course).  I'll download a new one.

> 
>   The second sync instruction ensures completion of all prior icbi
>   instructions.  Note that the second sync instruction is not shown in
>   Section 5.1.5.2, Instruction Cache Instructions, in The Programming
>   Environments Manual.  This sync is required on the MPC7451.
> 
> It is not clear if this is a recognized errata for only this processor
> revision or if this instruction was always supposed to be required.

There's an equivalent section (3.5.3.8) in the 7410 UM, too.

> 
> Anyway, under the circumstances I guess we have no choice but to add
> the extra sync to support this processor.  I'll do this when I commit
> Steven's patch.

Thanks,


Segher