This is the mail archive of the
glibc-cvs@sourceware.org
mailing list for the glibc project.
GNU C Library master sources branch master updated. glibc-2.26.9000-1132-g207a72e
- From: hjl at sourceware dot org
- To: glibc-cvs at sourceware dot org
- Date: 17 Jan 2018 12:32:30 -0000
- Subject: GNU C Library master sources branch master updated. glibc-2.26.9000-1132-g207a72e
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "GNU C Library master sources".
The branch, master has been updated
via 207a72e2988c6d6343f50fe0128eb4fc4edfdd15 (commit)
from 4942c4ea48099b4ba9dfecf7cfbc452ae74811b5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=207a72e2988c6d6343f50fe0128eb4fc4edfdd15
commit 207a72e2988c6d6343f50fe0128eb4fc4edfdd15
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Wed Jan 17 04:31:51 2018 -0800
x86-64: Properly align La_x86_64_retval to VEC_SIZE [BZ #22715]
_dl_runtime_profile calls _dl_call_pltexit, passing a pointer to
La_x86_64_retval which is allocated on stack. The lrv_vector0
field in La_x86_64_retval must be aligned to size of vector register.
When allocating stack space for La_x86_64_retval, we need to make sure
that the address of La_x86_64_retval + RV_VECTOR0_OFFSET is aligned to
VEC_SIZE. This patch checks the alignment of the lrv_vector0 field
and pads the stack space if needed.
Tested with x32 and x86-64 on SSE4, AVX and AVX512 machines. It fixed
FAIL: elf/tst-audit10
FAIL: elf/tst-audit4
FAIL: elf/tst-audit5
FAIL: elf/tst-audit6
FAIL: elf/tst-audit7
on x32 AVX512 machine.
[BZ #22715]
* sysdeps/x86_64/dl-trampoline.h (_dl_runtime_profile): Properly
align La_x86_64_retval to VEC_SIZE.
diff --git a/ChangeLog b/ChangeLog
index 42f871e..aed3cdf 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2018-01-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ [BZ #22715]
+ * sysdeps/x86_64/dl-trampoline.h (_dl_runtime_profile): Properly
+ align La_x86_64_retval to VEC_SIZE.
+
2018-01-16 Joseph Myers <joseph@codesourcery.com>
* sysdeps/x86_64/backtrace.c: Include <gnu/lib-names.h>.
diff --git a/sysdeps/x86_64/dl-trampoline.h b/sysdeps/x86_64/dl-trampoline.h
index 15edf49..298cfb3 100644
--- a/sysdeps/x86_64/dl-trampoline.h
+++ b/sysdeps/x86_64/dl-trampoline.h
@@ -440,8 +440,16 @@ _dl_runtime_profile:
# ifdef RESTORE_AVX
/* sizeof(La_x86_64_retval). Need extra space for 2 SSE
registers to detect if xmm0/xmm1 registers are changed
- by audit module. */
- sub $(LRV_SIZE + XMM_SIZE*2), %RSP_LP
+ by audit module. Since rsp is aligned to VEC_SIZE, we
+ need to make sure that the address of La_x86_64_retval +
+ LRV_VECTOR0_OFFSET is aligned to VEC_SIZE. */
+# define LRV_SPACE (LRV_SIZE + XMM_SIZE*2)
+# define LRV_MISALIGNED ((LRV_SIZE + LRV_VECTOR0_OFFSET) & (VEC_SIZE - 1))
+# if LRV_MISALIGNED == 0
+ sub $LRV_SPACE, %RSP_LP
+# else
+ sub $(LRV_SPACE + VEC_SIZE - LRV_MISALIGNED), %RSP_LP
+# endif
# else
sub $LRV_SIZE, %RSP_LP # sizeof(La_x86_64_retval)
# endif
-----------------------------------------------------------------------
Summary of changes:
ChangeLog | 6 ++++++
sysdeps/x86_64/dl-trampoline.h | 12 ++++++++++--
2 files changed, 16 insertions(+), 2 deletions(-)
hooks/post-receive
--
GNU C Library master sources