This is the mail archive of the glibc-cvs@sourceware.org mailing list for the glibc project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

GNU C Library master sources branch master updated. glibc-2.23-341-gde71e04


This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "GNU C Library master sources".

The branch, master has been updated
       via  de71e0421b4e267f9b6cf5a827ee5bab70226cd9 (commit)
      from  7c08d791ee4fabf96d96b66dec803602e621057c (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=de71e0421b4e267f9b6cf5a827ee5bab70226cd9

commit de71e0421b4e267f9b6cf5a827ee5bab70226cd9
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Thu May 19 10:02:36 2016 -0700

    Correct Intel processor level type mask from CPUID
    
    Intel CPUID with EAX == 11 returns:
    
    ECX Bits 07 - 00: Level number. Same value in ECX input.
        Bits 15 - 08: Level type.
        ^^^^^^^^^^^^^^^^^^^^^^^^ This is level type.
        Bits 31 - 16: Reserved.
    
    Intel processor level type mask should be 0xff00, not 0xff0.
    
    	[BZ #20119]
    	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
    	processor level type mask for CPUID with EAX == 11.

diff --git a/ChangeLog b/ChangeLog
index 8adf828..7ba904d 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,11 @@
 2016-05-19  H.J. Lu  <hongjiu.lu@intel.com>
 
+	[BZ #20119]
+	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
+	processor level type mask for CPUID with EAX == 11.
+
+2016-05-19  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting
 	logical threads if the HTT bit is 0.
 	* sysdeps/x86/cpu-features.h (bit_cpu_HTT): New.
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 1f46d9d..020d3fd 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -552,7 +552,7 @@ init_cacheinfo (void)
 		      __cpuid_count (11, i++, eax, ebx, ecx, edx);
 
 		      int shipped = ebx & 0xff;
-		      int type = ecx & 0xff0;
+		      int type = ecx & 0xff00;
 		      if (shipped == 0 || type == 0)
 			break;
 		      else if (type == 0x200)

-----------------------------------------------------------------------

Summary of changes:
 ChangeLog               |    6 ++++++
 sysdeps/x86/cacheinfo.c |    2 +-
 2 files changed, 7 insertions(+), 1 deletions(-)


hooks/post-receive
-- 
GNU C Library master sources


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]