This is the mail archive of the
glibc-cvs@sourceware.org
mailing list for the glibc project.
GNU C Library master sources branch roland/arm-avoid-pc created. glibc-2.17-383-g0c61401
- From: roland at sourceware dot org
- To: glibc-cvs at sourceware dot org
- Date: 11 Mar 2013 23:46:53 -0000
- Subject: GNU C Library master sources branch roland/arm-avoid-pc created. glibc-2.17-383-g0c61401
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "GNU C Library master sources".
The branch, roland/arm-avoid-pc has been created
at 0c614015e32b634c5a2f0b82a7c5938904bb2204 (commit)
- Log -----------------------------------------------------------------
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=0c614015e32b634c5a2f0b82a7c5938904bb2204
commit 0c614015e32b634c5a2f0b82a7c5938904bb2204
Author: Roland McGrath <roland@hack.frob.com>
Date: Mon Mar 11 14:29:25 2013 -0700
ARM: Handle ARM_ALWAYS_BX in {add,sub}_n.S code.
diff --git a/ports/ChangeLog.arm b/ports/ChangeLog.arm
index 4a94b62..ec8ea48 100644
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@ -1,5 +1,8 @@
2013-03-11 Roland McGrath <roland@hack.frob.com>
+ * sysdeps/arm/add_n.S: Include <arm-features.h>.
+ [ARM_ALWAYS_BX]: Don't pop into pc.
+
* sysdeps/arm/arm-features.h (ARM_BX_ALIGN_LOG2): New macro.
* sysdeps/arm/memcpy.S: Respect ARM_BX_ALIGN_LOG2.
* sysdeps/arm/memmove.S: Likewise.
diff --git a/ports/sysdeps/arm/add_n.S b/ports/sysdeps/arm/add_n.S
index 119a994..52927d9 100644
--- a/ports/sysdeps/arm/add_n.S
+++ b/ports/sysdeps/arm/add_n.S
@@ -17,6 +17,7 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
+#include <arm-features.h>
.syntax unified
.text
@@ -80,5 +81,10 @@ ENTRY (FUNC)
9:
RETC /* copy carry out */
+#ifndef ARM_ALWAYS_BX
pop { r4, r5, r6, r7, r8, r10, pc }
+#else
+ pop { r4, r5, r6, r7, r8, r10, lr }
+ bx lr
+#endif
END (FUNC)
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=ee3f4a89408d2bf04082b1733c7d1ccb535dde02
commit ee3f4a89408d2bf04082b1733c7d1ccb535dde02
Author: Roland McGrath <roland@hack.frob.com>
Date: Mon Mar 11 09:32:40 2013 -0700
ARM_BX_ALIGN_LOG2
diff --git a/ports/ChangeLog.arm b/ports/ChangeLog.arm
index 61fc5cc..4a94b62 100644
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@ -1,5 +1,9 @@
2013-03-11 Roland McGrath <roland@hack.frob.com>
+ * sysdeps/arm/arm-features.h (ARM_BX_ALIGN_LOG2): New macro.
+ * sysdeps/arm/memcpy.S: Respect ARM_BX_ALIGN_LOG2.
+ * sysdeps/arm/memmove.S: Likewise.
+
* sysdeps/arm/arm-features.h: Add comment about ARM_ALWAYS_BX.
* sysdeps/arm/memcpy.S: Include <arm-features.h>.
[ARM_ALWAYS_BX]: Avoid pc as destination.
diff --git a/ports/sysdeps/arm/arm-features.h b/ports/sysdeps/arm/arm-features.h
index 139a403..921a1c7 100644
--- a/ports/sysdeps/arm/arm-features.h
+++ b/ports/sysdeps/arm/arm-features.h
@@ -40,4 +40,12 @@
that instructions using pc as a destination register must never be used,
so a "bx" (or "blx") instruction is always required. */
+/* The log2 of the minimum alignment required for an address that
+ is the target of a computed branch (i.e. a "bx" instruction).
+ A more-specific arm-features.h file may define this to set a more
+ stringent requirement. */
+#ifndef ARM_BX_ALIGN_LOG2
+# define ARM_BX_ALIGN_LOG2 2
+#endif
+
#endif /* arm-features.h */
diff --git a/ports/sysdeps/arm/memcpy.S b/ports/sysdeps/arm/memcpy.S
index c8c14b4..e3032a5 100644
--- a/ports/sysdeps/arm/memcpy.S
+++ b/ports/sysdeps/arm/memcpy.S
@@ -91,9 +91,9 @@ ENTRY(memcpy)
CALGN( adr r4, 6f )
CALGN( subs r2, r2, r3 ) @ C gets set
#ifndef ARM_ALWAYS_BX
- CALGN( add pc, r4, ip )
+ CALGN( add pc, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
#else
- CALGN( add r4, r4, ip )
+ CALGN( add r4, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
CALGN( bx r4 )
#endif
@@ -115,38 +115,55 @@ ENTRY(memcpy)
5: ands ip, r2, #28
rsb ip, ip, #32
#ifndef ARM_ALWAYS_BX
- addne pc, pc, ip @ C is always clear here
+ /* C is always clear here. */
+ addne pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
b 7f
#else
beq 7f
push {r10}
cfi_adjust_cfa_offset (4)
- add r10, pc, ip
+ add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
bx r10
#endif
+ .p2align ARM_BX_ALIGN_LOG2
6: nop
+ .p2align ARM_BX_ALIGN_LOG2
ldr r3, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r4, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r5, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r6, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r7, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr r8, [r1], #4
+ .p2align ARM_BX_ALIGN_LOG2
ldr lr, [r1], #4
#ifndef ARM_ALWAYS_BX
- add pc, pc, ip
+ add pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
nop
#else
- add r10, pc, ip
+ add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
bx r10
#endif
+ .p2align ARM_BX_ALIGN_LOG2
nop
+ .p2align ARM_BX_ALIGN_LOG2
str r3, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r4, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r5, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r6, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r7, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str r8, [r0], #4
+ .p2align ARM_BX_ALIGN_LOG2
str lr, [r0], #4
#ifdef ARM_ALWAYS_BX
diff --git a/ports/sysdeps/arm/memmove.S b/ports/sysdeps/arm/memmove.S
index 0cc8ab8..003e383 100644
--- a/ports/sysdeps/arm/memmove.S
+++ b/ports/sysdeps/arm/memmove.S
@@ -107,9 +107,9 @@ ENTRY(memmove)
CALGN( adr r4, 6f )
CALGN( subs r2, r2, ip ) @ C is set here
#ifndef ARM_ALWAYS_BX
- CALGN( add pc, r4, ip )
+ CALGN( add pc, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
#else
- CALGN( add r4, r4, ip )
+ CALGN( add r4, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
CALGN( bx r4 )
#endif
@@ -131,38 +131,55 @@ ENTRY(memmove)
5: ands ip, r2, #28
rsb ip, ip, #32
#ifndef ARM_ALWAYS_BX
- addne pc, pc, ip @ C is always clear here
+ /* C is always clear here. */
+ addne pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
b 7f
#else
beq 7f
push {r10}
cfi_adjust_cfa_offset (4)
- add r10, pc, ip
+ add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
bx r10
#endif
+ .p2align ARM_BX_ALIGN_LOG2
6: nop
+ .p2align ARM_BX_ALIGN_LOG2
ldr r3, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r4, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r5, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r6, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r7, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr r8, [r1, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
ldr lr, [r1, #-4]!
#ifndef ARM_ALWAYS_BX
- add pc, pc, ip
+ add pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
nop
#else
- add r10, pc, ip
+ add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
bx r10
#endif
+ .p2align ARM_BX_ALIGN_LOG2
nop
+ .p2align ARM_BX_ALIGN_LOG2
str r3, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r4, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r5, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r6, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r7, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str r8, [r0, #-4]!
+ .p2align ARM_BX_ALIGN_LOG2
str lr, [r0, #-4]!
#ifdef ARM_ALWAYS_BX
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=731aa5972a3e4fb1c550a4c3bec8d4f56d115686
commit 731aa5972a3e4fb1c550a4c3bec8d4f56d115686
Author: Roland McGrath <roland@hack.frob.com>
Date: Mon Mar 11 13:22:37 2013 -0700
ARM: Support avoiding pc as destination register.
diff --git a/ports/ChangeLog.arm b/ports/ChangeLog.arm
index 9db0b1b..61fc5cc 100644
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@ -1,5 +1,12 @@
2013-03-11 Roland McGrath <roland@hack.frob.com>
+ * sysdeps/arm/arm-features.h: Add comment about ARM_ALWAYS_BX.
+ * sysdeps/arm/memcpy.S: Include <arm-features.h>.
+ [ARM_ALWAYS_BX]: Avoid pc as destination.
+ * sysdeps/arm/memmove.S: Likewise.
+
+2013-03-11 Roland McGrath <roland@hack.frob.com>
+
* sysdeps/arm/bits/setjmp.h: Test [!__ASSEMBLER__] rather than [!_ASM].
* sysdeps/arm/jmpbuf-offsets.h: File removed.
* sysdeps/arm/jmpbuf-unwind.h: Don't #include it.
diff --git a/ports/sysdeps/arm/arm-features.h b/ports/sysdeps/arm/arm-features.h
index 31801cf..139a403 100644
--- a/ports/sysdeps/arm/arm-features.h
+++ b/ports/sysdeps/arm/arm-features.h
@@ -36,4 +36,8 @@
at runtime (or that we never care about its state) and so need not
be checked for. */
+/* A more-specific arm-features.h file may define ARM_ALWAYS_BX to indicate
+ that instructions using pc as a destination register must never be used,
+ so a "bx" (or "blx") instruction is always required. */
+
#endif /* arm-features.h */
diff --git a/ports/sysdeps/arm/memcpy.S b/ports/sysdeps/arm/memcpy.S
index eb9699d..c8c14b4 100644
--- a/ports/sysdeps/arm/memcpy.S
+++ b/ports/sysdeps/arm/memcpy.S
@@ -20,6 +20,7 @@
/* Thumb requires excessive IT insns here. */
#define NO_THUMB
#include <sysdep.h>
+#include <arm-features.h>
/*
* Data preload for architectures that support it (ARM V5TE and above)
@@ -89,7 +90,12 @@ ENTRY(memcpy)
CALGN( bcs 2f )
CALGN( adr r4, 6f )
CALGN( subs r2, r2, r3 ) @ C gets set
+#ifndef ARM_ALWAYS_BX
CALGN( add pc, r4, ip )
+#else
+ CALGN( add r4, r4, ip )
+ CALGN( bx r4 )
+#endif
PLD( pld [r1, #0] )
2: PLD( subs r2, r2, #96 )
@@ -108,8 +114,16 @@ ENTRY(memcpy)
5: ands ip, r2, #28
rsb ip, ip, #32
+#ifndef ARM_ALWAYS_BX
addne pc, pc, ip @ C is always clear here
b 7f
+#else
+ beq 7f
+ push {r10}
+ cfi_adjust_cfa_offset (4)
+ add r10, pc, ip
+ bx r10
+#endif
6: nop
ldr r3, [r1], #4
ldr r4, [r1], #4
@@ -119,8 +133,13 @@ ENTRY(memcpy)
ldr r8, [r1], #4
ldr lr, [r1], #4
+#ifndef ARM_ALWAYS_BX
add pc, pc, ip
nop
+#else
+ add r10, pc, ip
+ bx r10
+#endif
nop
str r3, [r0], #4
str r4, [r0], #4
@@ -130,6 +149,11 @@ ENTRY(memcpy)
str r8, [r0], #4
str lr, [r0], #4
+#ifdef ARM_ALWAYS_BX
+ pop {r10}
+ cfi_adjust_cfa_offset (-4)
+#endif
+
CALGN( bcs 2b )
7: pop {r5 - r8}
@@ -147,7 +171,8 @@ ENTRY(memcpy)
strbcs r4, [r0], #1
strbcs ip, [r0]
-#if defined (__ARM_ARCH_4T__) && defined(__THUMB_INTERWORK__)
+#if ((defined (__ARM_ARCH_4T__) && defined(__THUMB_INTERWORK__)) \
+ || defined (ARM_ALWAYS_BX))
pop {r0, r4, lr}
cfi_adjust_cfa_offset (-12)
cfi_restore (r4)
diff --git a/ports/sysdeps/arm/memmove.S b/ports/sysdeps/arm/memmove.S
index 9e8ad65..0cc8ab8 100644
--- a/ports/sysdeps/arm/memmove.S
+++ b/ports/sysdeps/arm/memmove.S
@@ -20,6 +20,7 @@
/* Thumb requires excessive IT insns here. */
#define NO_THUMB
#include <sysdep.h>
+#include <arm-features.h>
/*
* Data preload for architectures that support it (ARM V5TE and above)
@@ -105,7 +106,12 @@ ENTRY(memmove)
CALGN( bcs 2f )
CALGN( adr r4, 6f )
CALGN( subs r2, r2, ip ) @ C is set here
+#ifndef ARM_ALWAYS_BX
CALGN( add pc, r4, ip )
+#else
+ CALGN( add r4, r4, ip )
+ CALGN( bx r4 )
+#endif
PLD( pld [r1, #-4] )
2: PLD( subs r2, r2, #96 )
@@ -124,8 +130,16 @@ ENTRY(memmove)
5: ands ip, r2, #28
rsb ip, ip, #32
+#ifndef ARM_ALWAYS_BX
addne pc, pc, ip @ C is always clear here
b 7f
+#else
+ beq 7f
+ push {r10}
+ cfi_adjust_cfa_offset (4)
+ add r10, pc, ip
+ bx r10
+#endif
6: nop
ldr r3, [r1, #-4]!
ldr r4, [r1, #-4]!
@@ -135,8 +149,13 @@ ENTRY(memmove)
ldr r8, [r1, #-4]!
ldr lr, [r1, #-4]!
+#ifndef ARM_ALWAYS_BX
add pc, pc, ip
nop
+#else
+ add r10, pc, ip
+ bx r10
+#endif
nop
str r3, [r0, #-4]!
str r4, [r0, #-4]!
@@ -146,6 +165,11 @@ ENTRY(memmove)
str r8, [r0, #-4]!
str lr, [r0, #-4]!
+#ifdef ARM_ALWAYS_BX
+ pop {r10}
+ cfi_adjust_cfa_offset (-4)
+#endif
+
CALGN( bcs 2b )
7: pop {r5 - r8}
@@ -163,7 +187,8 @@ ENTRY(memmove)
strbcs r4, [r0, #-1]!
strbcs ip, [r0, #-1]
-#if defined (__ARM_ARCH_4T__) && defined (__THUMB_INTERWORK__)
+#if ((defined (__ARM_ARCH_4T__) && defined (__THUMB_INTERWORK__)) \
+ || defined (ARM_ALWAYS_BX))
pop {r0, r4, lr}
cfi_adjust_cfa_offset (-12)
cfi_restore (r4)
-----------------------------------------------------------------------
hooks/post-receive
--
GNU C Library master sources