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[Bug libc/18185] Wrong processor count for L2 cache sharing on Silvermont and Knights Landing
- From: "cvs-commit at gcc dot gnu.org" <sourceware-bugzilla at sourceware dot org>
- To: glibc-bugs at sourceware dot org
- Date: Tue, 07 Jun 2016 16:09:02 +0000
- Subject: [Bug libc/18185] Wrong processor count for L2 cache sharing on Silvermont and Knights Landing
- Auto-submitted: auto-generated
- References: <bug-18185-131 at http dot sourceware dot org/bugzilla/>
https://sourceware.org/bugzilla/show_bug.cgi?id=18185
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The branch, hjl/erms/2.23 has been updated
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- Log -----------------------------------------------------------------
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=5a4f52493bc18322749ab15c4f5ae8deb7977201
commit 5a4f52493bc18322749ab15c4f5ae8deb7977201
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri May 27 15:16:22 2016 -0700
Count number of logical processors sharing L2 cache
For Intel processors, when there are both L2 and L3 caches, SMT level
type should be ued to count number of available logical processors
sharing L2 cache. If there is only L2 cache, core level type should
be used to count number of available logical processors sharing L2
cache. Number of available logical processors sharing L2 cache should
be used for non-inclusive L2 and L3 caches.
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of
available logical processors with SMT level type sharing L2
cache for Intel processors.
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=5879566b641cf573099ce9200eb44148e40b9b34
commit 5879566b641cf573099ce9200eb44148e40b9b34
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri May 20 14:41:14 2016 -0700
Remove special L2 cache case for Knights Landing
L2 cache is shared by 2 cores on Knights Landing, which has 4 threads
per core:
https://en.wikipedia.org/wiki/Xeon_Phi#Knights_Landing
So L2 cache is shared by 8 threads on Knights Landing as reported by
CPUID. We should remove special L2 cache case for Knights Landing.
[BZ #18185]
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Don't limit threads
sharing L2 cache to 2 for Knights Landing.
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=756fa392db3930cec9330169aef2c647df365432
commit 756fa392db3930cec9330169aef2c647df365432
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Thu May 19 10:02:36 2016 -0700
Correct Intel processor level type mask from CPUID
Intel CPUID with EAX == 11 returns:
ECX Bits 07 - 00: Level number. Same value in ECX input.
Bits 15 - 08: Level type.
^^^^^^^^^^^^^^^^^^^^^^^^ This is level type.
Bits 31 - 16: Reserved.
Intel processor level type mask should be 0xff00, not 0xff0.
[BZ #20119]
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
processor level type mask for CPUID with EAX == 11.
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=4c197f7a6b4ae1d57d1ad154ddae9db95b0abe86
commit 4c197f7a6b4ae1d57d1ad154ddae9db95b0abe86
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Thu May 19 09:09:00 2016 -0700
Check the HTT bit before counting logical threads
Skip counting logical threads for Intel processors if the HTT bit is 0
which indicates there is only a single logical processor.
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting
logical threads if the HTT bit is 0.
* sysdeps/x86/cpu-features.h (bit_cpu_HTT): New.
(index_cpu_HTT): Likewise.
(reg_HTT): Likewise.
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=5531ff0e927969eaf2f8fab12912e1a3a023ebc9
commit 5531ff0e927969eaf2f8fab12912e1a3a023ebc9
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Thu May 19 08:49:45 2016 -0700
Remove alignments on jump targets in memset
X86-64 memset-vec-unaligned-erms.S aligns many jump targets, which
increases code sizes, but not necessarily improve performance. As
memset benchtest data of align vs no align on various Intel and AMD
processors
https://sourceware.org/bugzilla/attachment.cgi?id=9277
shows that aligning jump targets isn't necessary.
[BZ #20115]
* sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S (__memset):
Remove alignments on jump targets.
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=2af76a7db8bc8eafccf3c78ec503283aa5249277
commit 2af76a7db8bc8eafccf3c78ec503283aa5249277
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri May 13 08:29:22 2016 -0700
Call init_cpu_features only if SHARED is defined
In static executable, since init_cpu_features is called early from
__libc_start_main, there is no need to call it again in dl_platform_init.
[BZ #20072]
* sysdeps/i386/dl-machine.h (dl_platform_init): Call
init_cpu_features only if SHARED is defined.
* sysdeps/x86_64/dl-machine.h (dl_platform_init): Likewise.
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=9c7a58e7f94cae195e85003b21c6bb7d2a0ec9a5
commit 9c7a58e7f94cae195e85003b21c6bb7d2a0ec9a5
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri May 13 07:18:25 2016 -0700
Support non-inclusive caches on Intel processors
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Check and support
non-inclusive caches on Intel processors.
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=9faebb60d146ade176ca5ad63e34ce67bacbec21
commit 9faebb60d146ade176ca5ad63e34ce67bacbec21
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Wed May 11 05:49:09 2016 -0700
Remove x86 ifunc-defines.sym and rtld-global-offsets.sym
Merge x86 ifunc-defines.sym with x86 cpu-features-offsets.sym. Remove
x86 ifunc-defines.sym and rtld-global-offsets.sym. No code changes on
i686 and x86-64.
* sysdeps/i386/i686/multiarch/Makefile (gen-as-const-headers):
Remove ifunc-defines.sym.
* sysdeps/x86_64/multiarch/Makefile (gen-as-const-headers):
Likewise.
* sysdeps/i386/i686/multiarch/ifunc-defines.sym: Removed.
* sysdeps/x86/rtld-global-offsets.sym: Likewise.
* sysdeps/x86_64/multiarch/ifunc-defines.sym: Likewise.
* sysdeps/x86/Makefile (gen-as-const-headers): Remove
rtld-global-offsets.sym.
* sysdeps/x86_64/multiarch/ifunc-defines.sym: Merged with ...
* sysdeps/x86/cpu-features-offsets.sym: This.
* sysdeps/x86/cpu-features.h: Include <cpu-features-offsets.h>
instead of <ifunc-defines.h> and <rtld-global-offsets.h>.
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=a29574292ac84a9882553aee676f0f5c73b064ed
commit a29574292ac84a9882553aee676f0f5c73b064ed
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Sun May 8 08:49:02 2016 -0700
Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86
Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86. No code changes on x86
and x86_64.
* sysdeps/i386/cacheinfo.c: Include <sysdeps/x86/cacheinfo.c>
instead of <sysdeps/x86_64/cacheinfo.c>.
* sysdeps/x86_64/cacheinfo.c: Moved to ...
* sysdeps/x86/cacheinfo.c: Here.
https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=601a5ed0cfe7ec825664ccd8112918f879eeeebc
commit 601a5ed0cfe7ec825664ccd8112918f879eeeebc
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri Apr 15 05:22:53 2016 -0700
Detect Intel Goldmont and Airmont processors
Updated from the model numbers of Goldmont and Airmont processors in
Intel64 And IA-32 Processor Architectures Software Developer's Manual
Volume 3 Revision 058.
* sysdeps/x86/cpu-features.c (init_cpu_features): Detect Intel
Goldmont and Airmont processors.
-----------------------------------------------------------------------
Summary of changes:
sysdeps/i386/cacheinfo.c | 2 +-
sysdeps/i386/dl-machine.h | 4 +
sysdeps/i386/i686/multiarch/Makefile | 1 -
sysdeps/i386/i686/multiarch/ifunc-defines.sym | 19 --
sysdeps/x86/Makefile | 2 +-
sysdeps/{x86_64 => x86}/cacheinfo.c | 244 ++++++++++++++------
sysdeps/x86/cpu-features-offsets.sym | 16 ++
sysdeps/x86/cpu-features.c | 8 +
sysdeps/x86/cpu-features.h | 6 +-
sysdeps/x86/rtld-global-offsets.sym | 7 -
sysdeps/x86_64/dl-machine.h | 4 +
sysdeps/x86_64/multiarch/Makefile | 1 -
sysdeps/x86_64/multiarch/ifunc-defines.sym | 20 --
.../x86_64/multiarch/memset-vec-unaligned-erms.S | 37 +---
14 files changed, 213 insertions(+), 158 deletions(-)
delete mode 100644 sysdeps/i386/i686/multiarch/ifunc-defines.sym
rename sysdeps/{x86_64 => x86}/cacheinfo.c (79%)
delete mode 100644 sysdeps/x86/rtld-global-offsets.sym
delete mode 100644 sysdeps/x86_64/multiarch/ifunc-defines.sym
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