This is the mail archive of the glibc-bugs@sourceware.org mailing list for the glibc project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[Bug nptl/17351] New: No hardware with functional lock elision available


https://sourceware.org/bugzilla/show_bug.cgi?id=17351

            Bug ID: 17351
           Summary: No hardware with functional lock elision available
           Product: glibc
           Version: unspecified
            Status: NEW
          Severity: normal
          Priority: P2
         Component: nptl
          Assignee: unassigned at sourceware dot org
          Reporter: cedric.bail at free dot fr
                CC: drepper.fsp at gmail dot com

Intel has found an issue in the lock elision micro code and is rolling out a
microcode that disable it apparently for older haswell.

http://techreport.com/news/26911/errata-prompts-intel-to-disable-tsx-in-haswell-early-broadwell-cpus
http://anandtech.com/show/8376/intel-disables-tsx-instructions-erratum-found-in-haswell-haswelleep-broadwell
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v3-spec-update.pdf

People who did not update their microcode will have some weird/random issue
most likely when using a glibc build with elision. Arch Linux has concluded it
is not a software bug and it doesn't require to change their packaging
(https://bugs.archlinux.org/task/39631).

Please advise what is the proper solution to this problem, as it potentially
affect a lot of people who wont know where the problem come from.

-- 
You are receiving this mail because:
You are on the CC list for the bug.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]