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Re: [PATCH v2 1/3] arm64/sve: Fix missing SVE/FPSIMD endianness conversions
- From: Dave Martin <Dave dot Martin at arm dot com>
- To: Catalin Marinas <catalin dot marinas at arm dot com>
- Cc: Will Deacon <will dot deacon at arm dot com>, Peter Maydell <peter dot maydell at linaro dot org>, gdb at sourceware dot org, Zhang Lei <zhang dot lei at jp dot fujitsu dot com>, Julien Grall <julien dot grall at arm dot com>, Alan Hayward <alan dot hayward at arm dot com>, Alex Bennée <alex dot bennee at linaro dot org>, linux-arm-kernel at lists dot infradead dot org
- Date: Thu, 27 Jun 2019 16:18:01 +0100
- Subject: Re: [PATCH v2 1/3] arm64/sve: Fix missing SVE/FPSIMD endianness conversions
- References: <1560355234-25516-1-git-send-email-Dave.Martin@arm.com> <1560355234-25516-2-git-send-email-Dave.Martin@arm.com> <20190612172853.GA27039@fuggles.cambridge.arm.com> <20190627135112.GC9894@arrakis.emea.arm.com>
On Thu, Jun 27, 2019 at 02:51:13PM +0100, Catalin Marinas wrote:
> On Wed, Jun 12, 2019 at 06:28:53PM +0100, Will Deacon wrote:
> > On Wed, Jun 12, 2019 at 05:00:32PM +0100, Dave Martin wrote:
> > > The in-memory representation of SVE and FPSIMD registers is
> > > different: the FPSIMD V-registers are stored as single 128-bit
> > > host-endian values, whereas SVE registers are stored in an
> > > endianness-invariant byte order.
> > >
> > > This means that the two representations differ when running on a
> > > big-endian host. But we blindly copy data from one representation
> > > to another when converting between the two, resulting in the
> > > register contents being unintentionally byteswapped in certain
> > > situations. Currently this can be triggered by the first SVE
> > > instruction after a syscall, for example (though the potential
> > > trigger points may vary in future).
> > >
> > > So, fix the conversion functions fpsimd_to_sve(), sve_to_fpsimd()
> > > and sve_sync_from_fpsimd_zeropad() to swab where appropriate.
> > >
> > > There is no common swahl128() or swab128() that we could use here.
> > > Maybe it would be worth making this generic, but for now add a
> > > simple local hack.
> > >
> > > Since the byte order differences are exposed in ABI, also clarify
> > > the docuentation.
> > >
> > > Fixes: bc0ee4760364 ("arm64/sve: Core task context handling")
> > > Fixes: 8cd969d28fd2 ("arm64/sve: Signal handling support")
> > > Fixes: 43d4da2c45b2 ("arm64/sve: ptrace and ELF coredump support")
> > > Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> >
> > Thanks, Dave. I've picked this one up and pushed it out to our fixes branch
> > for 5.2. I assume Catalin will take the other two for 5.3.
>
> At least the second patch depends on the first one. So I'll postpone
> merging them until -rc1.
Yes, that should be fine. Those are cleanup, supplementary to the fix.
Thanks
---Dave