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Re: icache-dcache coherence on ARM

On 5/6/19 12:30 PM, Xiaozhu Meng wrote:
> Hi,
> I am reading gdb's source code to hopefully get answers for a question that
> I have in my other project.
> On ARM, the architecture does not guarantee that icache and dcache are
> coherent. When GDB writes a software breakpoint into the inferior's address
> space, is it possible that the inferior executes outdated code in icache
> and thus miss the software breakpoint?
> I try to search around the gdb code base to understand whether GDB flushes
> icache or not, but could not find answers.
> I appreciate any feedback!

I suspect that the cache flushing is done by the host OS kernel in response
to the write.  This is what happens on FreeBSD at least where any executable
page in a process written to via ptrace(PT_IO) has its i-cache flushed by this
code in sys/kern/sys_process.c in proc_rwmem():

                 * Now do the i/o move.
                error = uiomove_fromphys(&m, page_offset, len, uio);

                /* Make the I-cache coherent for breakpoints. */
                if (writing && error == 0) {
                        if (vm_map_check_protection(map, pageno, pageno +
                            PAGE_SIZE, VM_PROT_EXECUTE))
                                vm_sync_icache(map, uva, len);

John Baldwin

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