[binutils-gdb] RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0

[sergiodj+buildbot at sergiodj dot net]

*** TEST RESULTS FOR COMMIT 63a25ea0de6d2f6d45b26af8d9c808aa35962256 ***

Author: Andrew Waterman <andrew@sifive.com>
Branch: master
Commit: 63a25ea0de6d2f6d45b26af8d9c808aa35962256

RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0

These are all invalid instructions, so they should not disassemble.

opcodes/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * riscv-opc.c (match_c_addi16sp) : New function.
        (match_c_addi4spn): New function.
        (match_c_lui): Don't allow 0-immediate encodings.
        (riscv_opcodes) <addi>: Use the above functions.
        <add>: Likewise.
        <c.addi4spn>: Likewise.
        <c.addi16sp>: Likewise.

gas/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * testsuite/gas/riscv/c-addi16sp-fail.d: New test.
        testsuite/gas/riscv/c-addi16sp-fail.l: Likewise.
        testsuite/gas/riscv/c-addi16sp-fail.s: Likewise.
        testsuite/gas/riscv/c-addi4spn-fail.d: Likewise.
        testsuite/gas/riscv/c-addi4spn-fail.l: Likewise.
        testsuite/gas/riscv/c-addi4spn-fail.s: Likewise.
        testsuite/gas/riscv/riscv.exp: Add new tests.