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[binutils-gdb/gdb-7.12-branch] [AArch64] Match instruction "STP with base register" in prologue


*** TEST RESULTS FOR COMMIT ded7f5d81cab3eb02cca835f0c9bd9525f35f268 ***

Author: Yao Qi <yao.qi@linaro.org>
Branch: gdb-7.12-branch
Commit: ded7f5d81cab3eb02cca835f0c9bd9525f35f268

[AArch64] Match instruction "STP with base register" in prologue

Nowadays, we only match pre-indexed STP in prologue.  Due to the change
in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it
may generate "STP with base register" in prologue, which GDB doesn't
handle.  That is to say, previously GCC generates prologue like this,

 sub sp, sp, #490
 stp x29, x30, [sp, #-96]!
 mov x29, sp

with the gcc patch above, GCC generates prologue like like this,

 sub sp, sp, #4f0
 stp x29, x30, [sp]
 mov x29, sp

This patch is to teach GDB to recognize this instruction in prologue
analysis.

gdb:

2016-08-19  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
	based STP instruction.


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