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[binutils-gdb] sim: trace: add a basic cpu register class


*** TEST RESULTS FOR COMMIT fa8f87e53b68881c5e3aab296b517203407c4378 ***

Author: Mike Frysinger <vapier@gentoo.org>
Branch: master
Commit: fa8f87e53b68881c5e3aab296b517203407c4378

sim: trace: add a basic cpu register class
The bfin/msp430 ports already had trace logic set up for reading/writing
cpu registers, albeit using different unrelated levels (core & vpu).  Add
a proper register class for these and for other ports.


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