This is the mail archive of the
gdb-patches@sourceware.org
mailing list for the GDB project.
[PATCH] aarch64 sim adds C flag bug fix
- From: Jim Wilson <jim dot wilson at linaro dot org>
- To: gdb-patches at sourceware dot org
- Date: Sat, 25 Mar 2017 20:40:09 -0700
- Subject: [PATCH] aarch64 sim adds C flag bug fix
- Authentication-results: sourceware.org; auth=none
This fixes a problem where the C flag was incorrectly set when adding
a large negative value with a small positive value. The word signed
result needs to be cast to unsigned to avoid a sign extension before
comparing with the double word unsigned result.
The modified testcase fails without the patch and works with the
patch. This patch reduces GCC C testsuite unexpected failures from
1445 to 1439 (-6).
Jim
2017-03-25 Jim Wilson <jim.wilson@linaro.org>
sim/aarch64/
* simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
flag check.
sim/testsuite/sim/aarch64/
* adds.s: Add checks for values -2 and 1, where C is not set.
diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 8a8df7a..f0668ad 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -1650,7 +1650,7 @@ set_flags_for_add32 (sim_cpu *cpu, int32_t value1, int32_t value2)
if (result & (1 << 31))
flags |= N;
- if (uresult != result)
+ if (uresult != (uint32_t)result)
flags |= C;
if (sresult != result)
diff --git a/sim/testsuite/sim/aarch64/adds.s b/sim/testsuite/sim/aarch64/adds.s
index 2bc240c..fdea5a7 100644
--- a/sim/testsuite/sim/aarch64/adds.s
+++ b/sim/testsuite/sim/aarch64/adds.s
@@ -3,6 +3,7 @@
# Check the basic integer compare instructions: adds, adds64, subs, subs64.
# For add, check value pairs 1 and -1 (Z), -1 and -1 (N), 2 and -1 (C),
# and MIN_INT and -1 (V),
+# Also check -2 and 1 (not C).
# For sub, negate the second value.
.include "testutils.inc"
@@ -24,6 +25,10 @@
mov w1, #-1
adds w2, w0, w1
bvc .Lfailure
+ mov w0, #-2
+ mov w1, #1
+ adds w2, w0, w1
+ bcs .Lfailure
mov x0, #1
mov x1, #-1
@@ -41,6 +46,10 @@
mov x1, #-1
adds x2, x0, x1
bvc .Lfailure
+ mov x0, #-2
+ mov x1, #1
+ adds x2, x0, x1
+ bcs .Lfailure
mov w0, #1
mov w1, #1
@@ -58,6 +67,10 @@
mov w1, #1
subs w2, w0, w1
bvc .Lfailure
+ mov w0, #-2
+ mov w1, #-1
+ subs w2, w0, w1
+ bcs .Lfailure
mov x0, #1
mov x1, #1
@@ -75,6 +88,10 @@
mov x1, #1
subs x2, x0, x1
bvc .Lfailure
+ mov x0, #-2
+ mov x1, #-1
+ subs x2, x0, x1
+ bcs .Lfailure
pass
.Lfailure: