This is the mail archive of the gdb-patches@sourceware.org mailing list for the GDB project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

RE: [PATCH v1] Intel(R) MPX registers to the DWARF enumeration.


HJ and Joel,

I suppose those registers were in on an older version of the ABI. However, I see no need for the DWARF registers as well. 
Will implement as in the new document; they will be out.

Thanks and regards,
-Fred

-----Original Message-----
From: H.J. Lu [mailto:hjl.tools@gmail.com] 
Sent: Sunday, December 06, 2015 6:42 PM
To: Joel Brobecker
Cc: Tedeschi, Walfred; GDB
Subject: Re: [PATCH v1] Intel(R) MPX registers to the DWARF enumeration.

On Sun, Dec 6, 2015 at 8:35 AM, Joel Brobecker <brobecker@adacore.com> wrote:
>> Add registers as defined in the ABI adapted for MPX.
>> As presented at:
>> https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI
>>
>> 2013-05-06  Walfred Tedeschi  <walfred.tedeschi@intel.com>
>>
>>         * amd64-tdep.c (amd64_dwarf_regmap): Add mpx registers.
>>         * amd64-tdep.h (amd64_regnum): Add mpx registers.
>
> Small nit: should we spell "MPX"?
>
> BTW - the ABI document reference above seem to only indicate registers 
> 126-129 as "reserved" rather than bound registers 0-4.
> Is that normal?
>

We used to have DWARF register map for bound registers.  But it was determined that it isn't needed.  If it isn't true, we need to revisit it.


--
H.J.
Intel Deutschland GmbH
Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de
Managing Directors: Christin Eisenschmid, Christian Lamprechter
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]