Re: [PATCH] [AArch64] Mark single precision pseudo registers unavailable if invalid

[Pierre Langlois <pierre dot langlois at arm dot com>]

On 15/07/15 15:41, Yao Qi wrote:
> On 15/07/15 15:00, Yao Qi wrote:
>> ... when I read your patch, I am wondering why does aarch64 implement
>> gdbarch method pseudo_register_read_value rather than
>> pseudo_register_read.  If we implement the pseudo_register_read, the
>> caller will mark the value unavailable according to its return value.
>> pseudo_register_read_value was added to handle partially available
>> registers byhttps://sourceware.org/ml/gdb-patches/2011-07/msg00351.html
>> but I don't think of a case that some aarch64 register is partially
>> available.  Maybe, another fix to this problem is to implement
>> pseudo_register_read instead of pseudo_register_read_value.

Yes, it makes sense to me.  I don't think we should have partially
available V registers in any cases.  For example, reading the S0 register
just ignores the top-level bits of the Q0 register, but they are still
available to read through Q0.  And writing to S0 will clear the top-level
bits of Q0.  As it is implemented in aarch64_pseudo_write.

> 
> To be clear, your patch can be pushed in, as it is correct and fixes
> fails in tests.  We can discuss and implement pseudo_register_read
> rather than pseudo_register_read_value for aarch64 later in the
> follow-up patch.
> 

OK, I'll push it in and make sure pseudo_register_read works as expected in
a follow-up patch.

Thanks,
Pierre