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[RFA] Fix amd64 dwarf register number mapping
- From: "Pierre Muller" <pierre dot muller at ics-cnrs dot unistra dot fr>
- To: <gdb-patches at sourceware dot org>
- Date: Wed, 1 Oct 2014 18:10:47 +0200
- Subject: [RFA] Fix amd64 dwarf register number mapping
- Authentication-results: sourceware.org; auth=none
dwarf register number is defined in
"System V Application Binary Interface
AMD64 Architecture Processor Supplement
Draft Version 0.99.6"
The amd64_dwarf_regmap array
is missing the 8 MMX registers
in Figure 3.36: DWARF Register Number Mapping page 57.
This leads to a wrong value for the
registers past this point.
I don't know if there are already
cases where this really fixes a problem,
but it is nevertheless a valid correction.
Is this OK, or is there a valid reason for
this "miss"?
Pierre Muller
Pascal language maintainer of GDB
2014-10-01 Pierre Muller <muller@sourceware.org>
* amd64-tdep.c (amd64_dwarf_regmap array): Fix amd64 dwarf
register numbering, by adding missing MMX registers.
diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
index 7c8575a..b98bc5d 100644
--- a/gdb/amd64-tdep.c
+++ b/gdb/amd64-tdep.c
@@ -201,7 +201,11 @@ static int amd64_dwarf_regmap[] =
AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
- /* Control and Status Flags Register. */
+ /* MMX Registers 0 - 7. Currently not handled,
+ see "tdep->num_mmx_regs = 0;" below. */
+ -1, -1, -1, -1, -1, -1, -1, -1,
+
+ /* Control and Status Flags Register. */
AMD64_EFLAGS_REGNUM,
/* Selector Registers. */