This is the mail archive of the gdb-patches@sourceware.org mailing list for the GDB project.

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]

RFA: V850: Add support for FPU-3.0 multiply-add instructions to the SIM

From: Nick Clifton <nickc at redhat dot com>
To: gdb-patches at sourceware dot org
Date: Wed, 03 Apr 2013 16:48:38 +0100
Subject: RFA: V850: Add support for FPU-3.0 multiply-add instructions to the SIM

Hi Guys,

  I would like permission to apply the patch below.  It adds support for
  the V850 E3V5 FPU-3.0 multiply-add instructions (FMAF.S, FMSF.S,
  FNMAF.S and FNMSF.S) to the v850 simulator.

  Tested with no regressions using a v850-elf toolchain and a recently
  patched version of gcc which now generates these instructions.

Cheers
  Nick

sim/ChangeLog
2013-04-03  Nick Clifton  <nickc@redhat.com>

	* v850.igen ((FMAF.S): New pattern.
	(FMSF.S): Likewise.
	(FNMAF.S): Likewise.
	(FNMSF.S): Likewise.

Index: sim/v850/v850.igen
===================================================================
RCS file: /cvs/src/src/sim/v850/v850.igen,v
retrieving revision 1.13
diff -u -3 -p -r1.13 v850.igen
--- sim/v850/v850.igen	28 Jan 2013 10:06:51 -0000	1.13
+++ sim/v850/v850.igen	3 Apr 2013 14:55:37 -0000
@@ -2801,7 +2804,6 @@ rrrrr,111111,RRRRR + wwwww,10001101110:F
 // MADDF.S
 rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s
 *v850e2v3
-*v850e3v5
 "maddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
 {
   sim_fpu ans, wop1, wop2, wop3;
@@ -2823,6 +2825,30 @@ rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW
   TRACE_FP_RESULT_FPU1 (&ans);
 }
 
+// FMAF.S
+rrrrr,111111,RRRRR + wwwww,10011100000:F_I:::fmaf_s
+*v850e3v5
+"fmaf.s r<reg1>, r<reg2>, r<reg3>"
+{
+  sim_fpu ans, wop1, wop2, wop3;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop1, GR[reg1]);
+  sim_fpu_32to (&wop2, GR[reg2]);
+  sim_fpu_32to (&wop3, GR[reg3]);
+  TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+  status = sim_fpu_mul (&ans, &wop1, &wop2);
+  wop1 = ans;
+  status |= sim_fpu_add (&ans, &wop1, &wop3);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+  sim_fpu_to32 (&GR[reg3], &ans);
+  TRACE_FP_RESULT_FPU1 (&ans);
+}
+
 // MAXF.D
 rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d
 *v850e2v3
@@ -2978,7 +3004,6 @@ rrrrr,111111,RRRRR + wwwww,10001101010:F
 // MSUBF.S
 rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s
 *v850e2v3
-*v850e3v5
 "msubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
 {
   sim_fpu ans, wop1, wop2, wop3;
@@ -3001,6 +3026,31 @@ rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW
   TRACE_FP_RESULT_FPU1 (&ans);
 }
 
+// FMSF.S
+rrrrr,111111,RRRRR + wwwww,10011100010:F_I:::fmsf_s
+*v850e3v5
+"fmsf.s r<reg1>, r<reg2>, r<reg3>"
+{
+  sim_fpu ans, wop1, wop2, wop3;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop1, GR[reg1]);
+  sim_fpu_32to (&wop2, GR[reg2]);
+  sim_fpu_32to (&wop3, GR[reg3]);
+  TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+  status = sim_fpu_mul (&ans, &wop1, &wop2);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+  wop1 = ans;
+  status |= sim_fpu_sub (&ans, &wop1, &wop3);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+  sim_fpu_to32 (&GR[reg3], &ans);
+  TRACE_FP_RESULT_FPU1 (&ans);
+}
+
 // MULF.D
 rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d
 *v850e2v3
@@ -3088,7 +3138,6 @@ rrrrr,11111100001 + wwwww,10001001000:F_
 // NMADDF.S
 rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s
 *v850e2v3
-*v850e3v5
 "nmaddf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
 {
   sim_fpu ans, wop1, wop2, wop3;
@@ -3112,10 +3161,35 @@ rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW
   TRACE_FP_RESULT_FPU1 (&ans);
 }
 
+// FNMAF.S
+rrrrr,111111,RRRRR + wwwww,10011100100:F_I:::fnmaf_s
+*v850e3v5
+"fnmaf.s r<reg1>, r<reg2>, r<reg3>"
+{
+  sim_fpu ans, wop1, wop2, wop3;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop1, GR[reg1]);
+  sim_fpu_32to (&wop2, GR[reg2]);
+  sim_fpu_32to (&wop3, GR[reg3]);
+  TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+  status = sim_fpu_mul (&ans, &wop1, &wop2);
+  wop1 = ans;
+  status |= sim_fpu_add (&ans, &wop1, &wop3);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+  wop1 = ans;
+  status |= sim_fpu_neg (&ans, &wop1);
+
+  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+  sim_fpu_to32 (&GR[reg3], &ans);
+  TRACE_FP_RESULT_FPU1 (&ans);
+}
+
 // NMSUBF.S
 rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s
 *v850e2v3
-*v850e3v5
 "nmsubf.s r<reg1>, r<reg2>, r<reg3>, r<reg4>"
 {
   sim_fpu ans, wop1, wop2, wop3;
@@ -3140,6 +3214,33 @@ rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW
   TRACE_FP_RESULT_FPU1 (&ans);
 }
 
+// FNMSF.S
+rrrrr,111111,RRRRR + wwwww,10011100110:F_I:::fnmsf_s
+*v850e3v5
+"fnmsf.s r<reg1>, r<reg2>, r<reg3>"
+{
+  sim_fpu ans, wop1, wop2, wop3;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop1, GR[reg1]);
+  sim_fpu_32to (&wop2, GR[reg2]);
+  sim_fpu_32to (&wop3, GR[reg3]);
+  TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+  status = sim_fpu_mul (&ans, &wop1, &wop2);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+  wop1 = ans;
+  status |= sim_fpu_sub (&ans, &wop1, &wop3);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+  wop1 = ans;
+  status |= sim_fpu_neg (&ans, &wop1);
+
+  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+  sim_fpu_to32 (&GR[reg3], &ans);
+  TRACE_FP_RESULT_FPU1 (&ans);
+}
+
 // RECIPF.D
 rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d
 *v850e2v3

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]