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[PATCH] Fix gdb disassemble for power6/power7 instructions
- From: Edjunior Barbosa Machado <emachado at linux dot vnet dot ibm dot com>
- To: gdb-patches at sourceware dot org
- Cc: binutils at sourceware dot org, amodra at gmail dot com
- Date: Tue, 13 Nov 2012 03:45:40 -0200
- Subject: [PATCH] Fix gdb disassemble for power6/power7 instructions
Hi,
upstream gdb is unable to disassemble power6 and power7 instructions due to a
change on binutils (http://sourceware.org/ml/binutils/2012-03/msg00170.html). It
happens because powerpc_init_dialect() is currently being called before
disassembler_options is configured (it used to be called every time
print_insn_[little|big]_powerpc() was called). The patch below intends to fix
this issue moving the logic to set disassembler_options to
powerpc_init_dialect().
Moreover, with this patch, objdump is also able to disassemble power6 and power7
instructions without the additional parameter -M <option>.
Comments/sugggestions are welcome.
Thanks,
--
Edjunior
gdb/ChangeLog
2012-11-13 Edjunior Machado <emachado@linux.vnet.ibm.com>
* rs6000-tdep.c (gdb_print_insn_powerpc): Move logic to set
info->disassembler_options to binutils' powerpc_init_dialect().
opcodes/ChangeLog
2012-11-13 Edjunior Machado <emachado@linux.vnet.ibm.com>
* ppc-dis.c (powerpc_init_dialect): If not defined, set
info->disassembler_options to "any" or, if debugging an E500 binary,
to "e500x2".
---
gdb/rs6000-tdep.c | 15 ---------------
opcodes/ppc-dis.c | 15 +++++++++++++++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 1797cc5..07b81bc 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -3084,21 +3084,6 @@ find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
static int
gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
{
- if (!info->disassembler_options)
- {
- /* When debugging E500 binaries and disassembling code containing
- E500-specific (SPE) instructions, one sometimes sees AltiVec
- instructions instead. The opcode spaces for SPE instructions
- and AltiVec instructions overlap, and specifiying the "any" cpu
- looks for AltiVec instructions first. If we know we're
- debugging an E500 binary, however, we can specify the "e500x2"
- cpu and get much more sane disassembly output. */
- if (info->mach == bfd_mach_ppc_e500)
- info->disassembler_options = "e500x2";
- else
- info->disassembler_options = "any";
- }
-
if (info->endian == BFD_ENDIAN_BIG)
return print_insn_big_powerpc (memaddr, info);
else
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 03b3160..63b71e5 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -251,6 +251,21 @@ powerpc_init_dialect (struct disassemble_info *info)
if (priv == NULL)
priv = &private;
+ if (!info->disassembler_options)
+ {
+ /* When debugging E500 binaries and disassembling code containing
+ E500-specific (SPE) instructions, one sometimes sees AltiVec
+ instructions instead. The opcode spaces for SPE instructions
+ and AltiVec instructions overlap, and specifiying the "any" cpu
+ looks for AltiVec instructions first. If we know we're
+ debugging an E500 binary, however, we can specify the "e500x2"
+ cpu and get much more sane disassembly output. */
+ if (info->mach == bfd_mach_ppc_e500)
+ info->disassembler_options = "e500x2";
+ else
+ info->disassembler_options = "any";
+ }
+
arg = info->disassembler_options;
while (arg != NULL)
{
--
1.7.1