[patch] sim: bfin: fix typos in large constants in tests

[Mike Frysinger <vapier at gentoo dot org>]

the tests we imported from the ADI sim had a bunch of places that had too many 
numbers (i.e. 40 or 48 bits) which we loaded into 32bit regs.  since the 
assembler itself truncates the number (as the ISA has no support for this), 
we've been dropping the excess digits when we noticed.  drop from a few more 
places as pointed out by Hans-Peter Nilsson.
-mike

2012-03-25  Mike Frysinger  <vapier@gentoo.org>

	* c_dsp32mac_dr_a1a0.s: Change 0x12efbc5569 to 0xefbc5569.
	* c_dsp32mac_dr_a1a0_iutsh.s: Change 0x12efbc556 to 0x2efbc556.
	* c_dsp32mac_dr_a1a0_m.s: Change 0x12efbc5569 to 0xefbc5569.
	* c_dsp32shift_vmaxvmax.s: Change 0xa11002001 to 0x11002001.
	* c_dsp32shiftim_af_s.s: Change 0x3a1230001 to 0xa1230001.

--- sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s
+++ sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s
@@ -14,7 +14,7 @@
 	imm32 r1, 0xb2bcfec7;
 	imm32 r2, 0xc1348679;
 	imm32 r3, 0xd0049007;
-	imm32 r4, 0x12efbc5569;
+	imm32 r4, 0xefbc5569;
 	imm32 r5, 0xcd35560b;
 	imm32 r6, 0xe00c807d;
 	imm32 r7, 0xf78e9008;
--- sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s
+++ sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s
@@ -14,7 +14,7 @@
 	imm32 r1, 0xb2bcfec7;
 	imm32 r2, 0xc1348679;
 	imm32 r3, 0xd0049007;
-	imm32 r4, 0x12efbc556;
+	imm32 r4, 0x2efbc556;
 	imm32 r5, 0xcd35560b;
 	imm32 r6, 0xe00c807d;
 	imm32 r7, 0xf78e9008;
--- sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s
+++ sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s
@@ -14,7 +14,7 @@
 	imm32 r1, 0xb2bcfec7;
 	imm32 r2, 0xc1348679;
 	imm32 r3, 0xd0049007;
-	imm32 r4, 0x12efbc5569;
+	imm32 r4, 0xefbc5569;
 	imm32 r5, 0xcd35560b;
 	imm32 r6, 0xe00c807d;
 	imm32 r7, 0xf78e9008;
--- sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s
+++ sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s
@@ -33,7 +33,7 @@ CHECKREG r5, 0x71004300;
 CHECKREG r6, 0x81007100;
 CHECKREG r7, 0x19008100;
 
-imm32 r0, 0xa11002001;
+imm32 r0, 0x11002001;
 imm32 r1, 0xd2001001;
 imm32 r2, 0x14301302;
 imm32 r3, 0x43001003;
--- sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s
+++ sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s
@@ -33,7 +33,7 @@ CHECKREG r5, 0x80000000;
 CHECKREG r6, 0x80000000;
 CHECKREG r7, 0x80000000;
 
-imm32 r0, 0x3a1230001;
+imm32 r0, 0xa1230001;
 imm32 r1, 0x1e345678;
 imm32 r2, 0x23f56789;
 imm32 r3, 0x34db789a;

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