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Re: [PATCH-ppc 0/5] Add feature description for new VSX register set
On Fri, 2008-07-25 at 21:45 +0000, Joseph S. Myers wrote:
> On Fri, 25 Jul 2008, Thiago Jung Bauermann wrote:
>
> > On Fri, 2008-07-25 at 21:01 +0000, Joseph S. Myers wrote:
> > > On Fri, 25 Jul 2008, Luis Machado wrote:
> > > > This is a patch series to enable POWER7 VSX register set support in GDB.
> > > > The VSX registers' layout is as follows:
> > >
> > > Will IBM be making appropriate proposals regarding these registers in the
> > > Power.org ABI working group? The obvious things that need defining
> > > include DWARF debug/unwind information handling of the registers, and
> > > what's call-saved / call-clobbered, plus ABI handling of any new
> > > C-language datatypes.
> >
> > Regarding call-saved / call-clobbered there's no option really. VSX
> > registers follow the saved-ness of the registers they overlap with
> > (either floating point or altivec).
>
> So will some of the bits that don't overlap be call-saved? If so, they
> need setjmp/longjmp support and unwind support, including in the signal
> unwind code in GCC. I presume such patches to the other toolchain
> components will follow in due course if needed.
No, those bits will be volatile, thus will be call-clobbered.
As for the other toolchain components, probably there will be future
patches to address the needed changes.
For more information about the new register state:
http://ozlabs.org/pipermail/linuxppc-dev/2008-June/058098.html
Best regards,
Luis