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On Tue, 2004-11-09 at 17:37, cgd@broadcom.com wrote:
> At Tue, 09 Nov 2004 11:59:28 -0500, Andrew Cagney wrote:
> > > Once the legal issues are resolved on your end, will be it be
> > > acceptable from your POV to merge them all into mips.igen?
> > > Or do you believe they should always be separate?
> >
> > That's a technical question, as I shouldn't, I don't care!
>
> actually, i didn't ask that as a technical question. it's a question
> about the state of the expected copyright/license on mips.igen once
> the any current issues are resolved.
>
> from your response, it sounds like you think that merging everything
> together would be not-disallowed-by-you.
>
>
> so, mips folks, i think the only solution for now is:
>
> (1) mark everything mips32/mips64 in mips.igen with additional
> mips32r2/mips64r2 markers, but
>
> (2) keep the new instructions in a separate file, which i can merge
> later.
>
>
>
> chris
ok.. here we go again..
:)
whenever you are ready Andrew.
David
Index: ChangeLog
===================================================================
RCS file: /cvs/uberbaum/sim/mips/ChangeLog,v
retrieving revision 1.109
diff -c -p -r1.109 ChangeLog
*** ChangeLog 24 Sep 2004 20:28:24 -0000 1.109
--- ChangeLog 24 Nov 2004 17:02:01 -0000
***************
*** 1,3 ****
--- 1,18 ----
+ 2004-11-24 David Ung <davidu@mips.com>
+
+ * mips.igen: Added models mips32r2 and mips64r2. Tag all existing
+ instructions which are applicable to mips32r2/mips64r2.
+
+ * mips3264r2.igen: New file for mips 32/64 revision 2 specific
+ instructions.
+
+ * vr.igen: The following instructions: ror, rorv, dror, dror32,
+ drorv and their corresponding worker functions do_ror/dodror are
+ moved into mips.igen.
+
+ * configure.in: Add targets mipsisa32r2*-*-* and mipsisa64r2*-*-*
+ to use mips32r2/64r2 models.
+
2004-09-24 Monika Chaddha <monika@acmet.com>
Committed by Andrew Cagney.
Index: configure.in
===================================================================
RCS file: /cvs/uberbaum/sim/mips/configure.in,v
retrieving revision 1.8
diff -c -p -r1.8 configure.in
*** configure.in 19 Aug 2004 07:02:04 -0000 1.8
--- configure.in 24 Nov 2004 17:02:01 -0000
*************** case "${target}" in
*** 141,146 ****
--- 141,151 ----
sim_igen_filter="32,64,f"
sim_m16_filter="16"
;;
+ mipsisa32r2*-*-*) sim_gen=IGEN
+ sim_igen_machine="-M mips32r2"
+ sim_igen_filter="32,f"
+ sim_mach_default="mipsisa32r2"
+ ;;
mipsisa32*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips32"
sim_igen_filter="32,f"
*************** case "${target}" in
*** 151,156 ****
--- 156,166 ----
sim_igen_filter="32,64,f"
sim_mach_default="mips_sb1"
;;
+ mipsisa64r2*-*-*) sim_gen=IGEN
+ sim_igen_machine="-M mips64r2,mips3d"
+ sim_igen_filter="32,64,f"
+ sim_mach_default="mipsisa64r2"
+ ;;
mipsisa64*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64,mips3d"
sim_igen_filter="32,64,f"
Index: mips.igen
===================================================================
RCS file: /cvs/uberbaum/sim/mips/mips.igen,v
retrieving revision 1.57
diff -c -p -r1.57 mips.igen
*** mips.igen 10 Apr 2004 06:51:49 -0000 1.57
--- mips.igen 24 Nov 2004 17:02:01 -0000
***************
*** 45,51 ****
--- 45,53 ----
:model:::mipsIV:mips8000:
:model:::mipsV:mipsisaV:
:model:::mips32:mipsisa32:
+ :model:::mips32r2:mipsisa32r2:
:model:::mips64:mipsisa64:
+ :model:::mips64r2:mipsisa64r2:
// Vendor ISAs:
//
***************
*** 132,137 ****
--- 134,140 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 141,146 ****
--- 144,150 ----
:function:::address_word:loadstore_ea:address_word base, address_word
offset
*mips64:
+ *mips64r2:
{
#if 0 /* XXX FIXME: enable this only after some additional testing.
*/
/* If in user mode and UX is not set, use 32-bit compatibility
effective
***************
*** 178,183 ****
--- 182,188 ----
:function:::int:not_word_value:unsigned_word value
*mips32:
+ *mips32r2:
{
/* On MIPS32, since registers are 32-bits, there's no check to be
done. */
return 0;
***************
*** 185,190 ****
--- 190,196 ----
:function:::int:not_word_value:unsigned_word value
*mips64:
+ *mips64r2:
{
return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
}
***************
*** 212,218 ****
--- 218,226 ----
:function:::void:unpredictable:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
{
unpredictable_action (CPU, CIA);
}
***************
*** 300,306 ****
--- 308,316 ----
:function:::int:check_mt_hilo:hilo_history *history
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*r3900:
{
signed64 time = sim_events_time (SD);
***************
*** 322,328 ****
--- 332,340 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 392,398 ****
--- 404,412 ----
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*r3900:
{
/* FIXME: could record the fact that a stall occured if we want */
***************
*** 445,451 ****
--- 459,467 ----
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
{
signed64 time = sim_events_time (SD);
hi->op.timestamp = time;
***************
*** 468,479 ****
--- 484,498 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5400:
+ *vr5500:
{
// The check should be similar to mips64 for any with PX/UX bit
equivalents.
}
:function:::void:check_u64:instruction_word insn
*mips64:
+ *mips64r2:
{
#if 0 /* XXX FIXME: enable this only after some additional testing.
*/
if (UserMode && (SR & (status_UX|status_PX)) == 0)
***************
*** 486,492 ****
//
// MIPS Architecture:
//
! // CPU Instruction Set (mipsI - mipsV, mips32, mips64)
//
--- 505,511 ----
//
// MIPS Architecture:
//
! // CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
//
***************
*** 499,505 ****
--- 518,526 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 525,531 ****
--- 546,554 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 560,566 ****
--- 583,591 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 587,593 ****
--- 612,620 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 612,618 ****
--- 639,647 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 630,636 ****
--- 659,667 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 650,656 ****
--- 681,689 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 671,677 ****
--- 704,712 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 695,701 ****
--- 730,738 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 717,723 ****
--- 754,762 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 741,747 ****
--- 780,788 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 769,775 ****
--- 810,818 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 793,799 ****
--- 836,844 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 814,820 ****
--- 859,867 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 840,846 ****
--- 887,895 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 863,869 ****
--- 912,920 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 887,893 ****
--- 938,946 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 909,915 ****
--- 962,970 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 935,941 ****
--- 990,998 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 961,967 ****
--- 1018,1026 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 987,993 ****
--- 1046,1054 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1008,1014 ****
--- 1069,1077 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1032,1038 ****
--- 1095,1103 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1068,1074 ****
--- 1133,1141 ----
011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
"clo r<RD>, r<RS>"
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5500:
{
unsigned32 temp = GPR[RS];
***************
*** 1093,1099 ****
--- 1160,1168 ----
011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
"clz r<RD>, r<RS>"
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5500:
{
unsigned32 temp = GPR[RS];
***************
*** 1121,1126 ****
--- 1190,1196 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1142,1147 ****
--- 1212,1218 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1170,1175 ****
--- 1241,1247 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1192,1197 ****
--- 1264,1270 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1204,1209 ****
--- 1277,1283 ----
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
+ *mips64r2:
*vr5500:
{
unsigned64 temp = GPR[RS];
***************
*** 1228,1233 ****
--- 1302,1308 ----
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
+ *mips64r2:
*vr5500:
{
unsigned64 temp = GPR[RS];
***************
*** 1285,1290 ****
--- 1360,1366 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1325,1330 ****
--- 1401,1407 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1332,1339 ****
do_ddivu (SD_, RS, RT);
}
-
-
:function:::void:do_div:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
--- 1409,1414 ----
***************
*** 1368,1374 ****
--- 1443,1451 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1407,1413 ****
--- 1484,1492 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1416,1422 ****
}
-
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
unsigned64 lo;
--- 1495,1500 ----
***************
*** 1488,1493 ****
--- 1566,1572 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
{
check_u64 (SD_, instruction_0);
***************
*** 1516,1521 ****
--- 1595,1601 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
{
check_u64 (SD_, instruction_0);
***************
*** 1531,1536 ****
--- 1611,1659 ----
do_dmultu (SD_, RS, RT, RD);
}
+
+ :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
+ {
+ unsigned64 result;
+
+ y &= 63;
+ TRACE_ALU_INPUT2 (x, y);
+ result = ROTR64 (x, y);
+ TRACE_ALU_RESULT (result);
+ return result;
+ }
+
+ 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
+ "dror r<RD>, r<RT>, <SHIFT>"
+ *mips64r2:
+ *vr5400:
+ *vr5500:
+ {
+ check_u64 (SD_, instruction_0);
+ GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
+ }
+
+ 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
+ "dror32 r<RD>, r<RT>, <SHIFT>"
+ *mips64r2:
+ *vr5400:
+ *vr5500:
+ {
+ check_u64 (SD_, instruction_0);
+ GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
+ }
+
+ 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
+ "drorv r<RD>, r<RT>, r<RS>"
+ *mips64r2:
+ *vr5400:
+ *vr5500:
+ {
+ check_u64 (SD_, instruction_0);
+ GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
+ }
+
+
:function:::void:do_dsll:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
***************
*** 1544,1549 ****
--- 1667,1673 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1558,1563 ****
--- 1682,1688 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1582,1587 ****
--- 1707,1713 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1603,1608 ****
--- 1729,1735 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1617,1622 ****
--- 1744,1750 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1642,1647 ****
--- 1770,1776 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1663,1668 ****
--- 1792,1798 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1677,1682 ****
--- 1807,1813 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1704,1709 ****
--- 1835,1841 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1718,1723 ****
--- 1850,1856 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1745,1750 ****
--- 1878,1884 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1761,1767 ****
--- 1895,1903 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1781,1787 ****
--- 1917,1925 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1802,1808 ****
--- 1940,1948 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1821,1827 ****
--- 1961,1969 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1948,1954 ****
--- 2090,2098 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1965,1971 ****
--- 2109,2117 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 1980,1985 ****
--- 2126,2132 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 1995,2001 ****
--- 2142,2150 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2012,2017 ****
--- 2161,2167 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2026,2031 ****
--- 2176,2182 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2042,2048 ****
--- 2193,2201 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2059,2065 ****
--- 2212,2220 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2075,2081 ****
--- 2230,2238 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2117,2122 ****
--- 2274,2280 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2154,2160 ****
--- 2312,2320 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2173,2179 ****
--- 2333,2341 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2190,2196 ****
--- 2352,2360 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2207,2213 ****
--- 2371,2379 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2224,2230 ****
--- 2390,2398 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2239,2244 ****
--- 2407,2413 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2251,2257 ****
--- 2420,2428 ----
011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
"madd r<RS>, r<RT>"
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5500:
{
signed64 temp;
***************
*** 2271,2277 ****
--- 2442,2450 ----
011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
"maddu r<RS>, r<RT>"
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5500:
{
unsigned64 temp;
***************
*** 2303,2309 ****
--- 2476,2484 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2329,2335 ****
--- 2504,2512 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2344,2350 ****
--- 2521,2529 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5000:
{
if (GPR[RT] != 0)
***************
*** 2361,2367 ****
--- 2540,2548 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5000:
{
if (GPR[RT] == 0)
***************
*** 2376,2382 ****
--- 2557,2565 ----
011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
"msub r<RS>, r<RT>"
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5500:
{
signed64 temp;
***************
*** 2396,2402 ****
--- 2579,2587 ----
011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
"msubu r<RS>, r<RT>"
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5500:
{
unsigned64 temp;
***************
*** 2421,2427 ****
--- 2606,2614 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2440,2446 ****
--- 2627,2635 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2454,2460 ****
--- 2643,2651 ----
011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
"mul r<RD>, r<RS>, r<RT>"
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5500:
{
signed64 prod;
***************
*** 2493,2499 ****
--- 2684,2692 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
{
do_mult (SD_, RS, RT, 0);
***************
*** 2534,2540 ****
--- 2727,2735 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
{
do_multu (SD_, RS, RT, 0);
***************
*** 2565,2571 ****
--- 2760,2768 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2589,2595 ****
--- 2786,2794 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2614,2620 ****
--- 2813,2821 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2628,2634 ****
--- 2829,2837 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5000:
{
address_word base = GPR[BASE];
***************
*** 2645,2650 ****
--- 2848,2885 ----
}
+ :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
+ {
+ unsigned64 result;
+
+ y &= 31;
+ TRACE_ALU_INPUT2 (x, y);
+ result = EXTEND32 (ROTR32 (x, y));
+ TRACE_ALU_RESULT (result);
+ return result;
+ }
+
+ 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
+ "ror r<RD>, r<RT>, <SHIFT>"
+ *mips32r2:
+ *mips64r2:
+ *vr5400:
+ *vr5500:
+ {
+ GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
+ }
+
+ 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
+ "rorv r<RD>, r<RT>, r<RS>"
+ *mips32r2:
+ *mips64r2:
+ *vr5400:
+ *vr5500:
+ {
+ GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
+ }
+
+
:function:::void:do_store:unsigned access, address_word base,
address_word offset, unsigned_word word
{
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
***************
*** 2743,2749 ****
--- 2978,2986 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2759,2765 ****
--- 2996,3004 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2802,2807 ****
--- 3041,3047 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2840,2845 ****
--- 3080,3086 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2855,2861 ****
--- 3096,3104 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2869,2874 ****
--- 3112,3118 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2883,2888 ****
--- 3127,3133 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 2891,2896 ****
--- 3136,3142 ----
}
+
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
***************
*** 2899,2905 ****
--- 3145,3153 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2939,2945 ****
--- 3187,3195 ----
"ssnop":RD == 0 && RT == 0 && SHIFT == 1
"sll r<RD>, r<RT>, <SHIFT>"
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
{
/* Skip shift for NOP and SSNOP, so that there won't be lots of
extraneous trace output. */
***************
*** 2965,2971 ****
--- 3215,3223 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 2989,2995 ****
--- 3241,3249 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3013,3019 ****
--- 3267,3275 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3037,3043 ****
--- 3293,3301 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3062,3068 ****
--- 3320,3328 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3089,3095 ****
--- 3349,3357 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3118,3124 ****
--- 3380,3388 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3146,3152 ****
--- 3410,3418 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3174,3180 ****
--- 3440,3448 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3191,3197 ****
--- 3459,3467 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3225,3231 ****
--- 3495,3503 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3242,3248 ****
--- 3514,3522 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*r3900:
*vr5000:
***************
*** 3259,3265 ****
--- 3533,3541 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3276,3282 ****
--- 3552,3560 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3293,3299 ****
--- 3571,3579 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3310,3316 ****
--- 3590,3598 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3327,3333 ****
--- 3609,3617 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3343,3349 ****
--- 3627,3635 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3359,3365 ****
--- 3645,3653 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3375,3381 ****
--- 3663,3671 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3391,3397 ****
--- 3681,3689 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3407,3413 ****
--- 3699,3707 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3423,3429 ****
--- 3717,3725 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3439,3445 ****
--- 3735,3743 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3455,3461 ****
--- 3753,3761 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3471,3477 ****
--- 3771,3779 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3487,3493 ****
--- 3789,3797 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3503,3509 ****
--- 3807,3815 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3519,3525 ****
--- 3825,3833 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 3543,3549 ****
--- 3851,3859 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3567,3573 ****
--- 3877,3885 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3650,3655 ****
--- 3962,3968 ----
*mipsIII:
*mipsIV:
*mips32:
+ *mips32r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3663,3668 ****
--- 3976,3982 ----
:function:::void:check_fmt_p:int fmt, instruction_word insn
*mipsV:
*mips64:
+ *mips64r2:
{
if ((fmt != fmt_single) && (fmt != fmt_double)
&& (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX))
== 0)))
***************
*** 3683,3689 ****
--- 3997,4005 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3703,3708 ****
--- 4019,4025 ----
:function:::unsigned64:do_load_double:address_word base, address_word
offset
*mipsII:
*mips32:
+ *mips32r2:
{
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
address_word vaddr;
***************
*** 3739,3744 ****
--- 4056,4062 ----
:function:::void:do_store_double:address_word base, address_word
offset, unsigned64 v
*mipsII:
*mips32:
+ *mips32r2:
{
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
address_word vaddr;
***************
*** 3772,3778 ****
--- 4090,4098 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3793,3799 ****
--- 4113,4121 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3809,3814 ****
--- 4131,4137 ----
"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
*mipsV:
*mips64:
+ *mips64r2:
{
unsigned64 fs;
unsigned64 ft;
***************
*** 3868,3874 ****
--- 4191,4199 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
#*vr4100:
*vr5000:
*r3900:
***************
*** 3904,3910 ****
--- 4229,4237 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3923,3928 ****
--- 4250,4256 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3941,3947 ****
--- 4269,4277 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 3989,3995 ****
--- 4319,4327 ----
"cfc1 r<RT>, f<FS>"
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
{
check_fpu (SD_);
if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
***************
*** 4032,4038 ****
--- 4364,4372 ----
"ctc1 r<RT>, f<FS>"
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
{
check_fpu (SD_);
TRACE_ALU_INPUT1 (GPR[RT]);
***************
*** 4053,4059 ****
--- 4387,4395 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4073,4078 ****
--- 4409,4415 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4090,4095 ****
--- 4427,4433 ----
"cvt.ps.s f<FD>, f<FS>, f<FT>"
*mipsV:
*mips64:
+ *mips64r2:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
***************
*** 4109,4115 ****
--- 4447,4455 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4127,4132 ****
--- 4467,4473 ----
"cvt.s.pl f<FD>, f<FS>"
*mipsV:
*mips64:
+ *mips64r2:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
***************
*** 4138,4143 ****
--- 4479,4485 ----
"cvt.s.pu f<FD>, f<FS>"
*mipsV:
*mips64:
+ *mips64r2:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
***************
*** 4153,4159 ****
--- 4495,4503 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4175,4181 ****
--- 4519,4527 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4208,4213 ****
--- 4554,4560 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4248,4253 ****
--- 4595,4601 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4269,4274 ****
--- 4617,4623 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4287,4293 ****
--- 4636,4644 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4303,4308 ****
--- 4654,4660 ----
"ldc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsII:
*mips32:
+ *mips32r2:
{
check_fpu (SD_);
COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
***************
*** 4315,4320 ****
--- 4667,4673 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4329,4334 ****
--- 4682,4688 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
check_fpu (SD_);
***************
*** 4341,4346 ****
--- 4695,4701 ----
"luxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsV:
*mips64:
+ *mips64r2:
{
address_word base = GPR[BASE];
address_word index = GPR[INDEX];
***************
*** 4362,4368 ****
--- 4717,4725 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4377,4382 ****
--- 4734,4740 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
check_fpu (SD_);
***************
*** 4391,4396 ****
--- 4749,4755 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
int fmt = FMT;
***************
*** 4420,4426 ****
--- 4779,4787 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4439,4445 ****
--- 4800,4808 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4458,4464 ****
--- 4821,4829 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5000:
{
check_fpu (SD_);
***************
*** 4474,4480 ****
--- 4839,4847 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5000:
{
int fmt = FMT;
***************
*** 4503,4509 ****
--- 4870,4878 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5000:
{
check_fpu (SD_);
***************
*** 4526,4532 ****
--- 4895,4903 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr5000:
{
check_fpu (SD_);
***************
*** 4542,4547 ****
--- 4913,4919 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
int fmt = FMT;
***************
*** 4572,4578 ****
--- 4944,4952 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4590,4596 ****
--- 4964,4972 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4610,4616 ****
--- 4986,4994 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4627,4632 ****
--- 5005,5011 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
int fmt = FMT;
***************
*** 4643,4648 ****
--- 5022,5028 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
int fmt = FMT;
***************
*** 4658,4663 ****
--- 5038,5044 ----
"pll.ps f<FD>, f<FS>, f<FT>"
*mipsV:
*mips64:
+ *mips64r2:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
***************
*** 4670,4675 ****
--- 5051,5057 ----
"plu.ps f<FD>, f<FS>, f<FT>"
*mipsV:
*mips64:
+ *mips64r2:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
***************
*** 4683,4688 ****
--- 5065,5071 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
address_word base = GPR[BASE];
***************
*** 4701,4706 ****
--- 5084,5090 ----
"pul.ps f<FD>, f<FS>, f<FT>"
*mipsV:
*mips64:
+ *mips64r2:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
***************
*** 4713,4718 ****
--- 5097,5103 ----
"puu.ps f<FD>, f<FS>, f<FT>"
*mipsV:
*mips64:
+ *mips64r2:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
***************
*** 4726,4731 ****
--- 5111,5117 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
int fmt = FMT;
***************
*** 4740,4745 ****
--- 5126,5132 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4758,4764 ****
--- 5145,5153 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4775,4780 ****
--- 5164,5170 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
int fmt = FMT;
***************
*** 4787,4792 ****
--- 5177,5183 ----
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsII:
*mips32:
+ *mips32r2:
{
check_fpu (SD_);
do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
***************
*** 4799,4804 ****
--- 5190,5196 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4813,4818 ****
--- 5205,5211 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
check_fpu (SD_);
***************
*** 4825,4830 ****
--- 5218,5224 ----
"suxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsV:
*mips64:
+ *mips64r2:
{
unsigned64 v;
address_word base = GPR[BASE];
***************
*** 4846,4852 ****
--- 5240,5248 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4865,4871 ****
--- 5261,5269 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4886,4892 ****
--- 5284,5292 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4927,4932 ****
--- 5327,5333 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr5000:
{
***************
*** 4968,4973 ****
--- 5369,5375 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 4986,4992 ****
--- 5388,5396 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 5013,5019 ****
--- 5417,5425 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
***************
*** 5034,5040 ****
--- 5440,5448 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
***************
*** 5047,5053 ****
--- 5455,5463 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
***************
*** 5059,5065 ****
--- 5469,5477 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
***************
*** 5070,5076 ****
--- 5482,5490 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 5093,5098 ****
--- 5507,5513 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
***************
*** 5105,5110 ****
--- 5520,5526 ----
*mipsIV:
*mipsV:
*mips64:
+ *mips64r2:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
***************
*** 5117,5123 ****
--- 5533,5541 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
{
***************
*** 5144,5150 ****
--- 5562,5570 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 5162,5168 ****
--- 5582,5590 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
*r3900:
***************
*** 5194,5200 ****
--- 5616,5624 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*r3900:
{
***************
*** 5211,5217 ****
--- 5635,5643 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
***************
*** 5224,5230 ****
--- 5650,5658 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
***************
*** 5237,5243 ****
--- 5665,5673 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
***************
*** 5250,5264 ****
*mipsIV:
*mipsV:
*mips32:
*mips64:
*vr4100:
*vr5000:
!
:include:::m16.igen
:include:::mdmx.igen
:include:::mips3d.igen
:include:::sb1.igen
:include:::tx.igen
:include:::vr.igen
!
--- 5680,5697 ----
*mipsIV:
*mipsV:
*mips32:
+ *mips32r2:
*mips64:
+ *mips64r2:
*vr4100:
*vr5000:
!
! :include:::mips3264r2.igen
:include:::m16.igen
:include:::mdmx.igen
:include:::mips3d.igen
:include:::sb1.igen
:include:::tx.igen
:include:::vr.igen
!
Index: vr.igen
===================================================================
RCS file: /cvs/uberbaum/sim/mips/vr.igen,v
retrieving revision 1.3
diff -c -p -r1.3 vr.igen
*** vr.igen 16 Apr 2003 00:52:08 -0000 1.3
--- vr.igen 24 Nov 2004 17:02:01 -0000
***************
*** 100,134 ****
GPR[rd] = store_hi_p ? HI : LO;
}
- // 32-bit rotate right of X by Y bits.
- :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
- *vr5400:
- *vr5500:
- {
- unsigned64 result;
-
- y &= 31;
- TRACE_ALU_INPUT2 (x, y);
- result = EXTEND32 (ROTR32 (x, y));
- TRACE_ALU_RESULT (result);
- return result;
- }
-
- // Likewise 64-bit
- :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
- *vr5400:
- *vr5500:
- {
- unsigned64 result;
-
- y &= 63;
- TRACE_ALU_INPUT2 (x, y);
- result = ROTR64 (x, y);
- TRACE_ALU_RESULT (result);
- return result;
- }
-
-
// VR4100 instructions.
000000,5.RS,5.RT,00000,00000,101000::32::MADD16
--- 100,105 ----
***************
*** 246,290 ****
0 /* single */);
}
- 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
- "ror r<RD>, r<RT>, <SHIFT>"
- *vr5400:
- *vr5500:
- {
- GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
- }
-
- 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
- "rorv r<RD>, r<RT>, r<RS>"
- *vr5400:
- *vr5500:
- {
- GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
- }
-
- 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
- "dror r<RD>, r<RT>, <SHIFT>"
- *vr5400:
- *vr5500:
- {
- GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
- }
-
- 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
- "dror32 r<RD>, r<RT>, <SHIFT>"
- *vr5400:
- *vr5500:
- {
- GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
- }
-
- 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
- "drorv r<RD>, r<RT>, r<RS>"
- *vr5400:
- *vr5500:
- {
- GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
- }
010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1
"luxc1 f<FD>, r<INDEX>(r<BASE>)"
--- 217,222 ----
Attachment:
mips3264r2.igen
Description: Text document
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