This is the mail archive of the
gdb-patches@sources.redhat.com
mailing list for the GDB project.
[PATCH] whitespace / comments in sim/sh/gencode.c
- From: Michael Snyder <msnyder at redhat dot com>
- To: Joern Rennecke <joern dot rennecke at superh dot com>
- Cc: gdb-patches at sources dot redhat dot com
- Date: Tue, 27 Jan 2004 15:27:03 -0800
- Subject: [PATCH] whitespace / comments in sim/sh/gencode.c
- Organization: Red Hat, Inc.
Accumulated trivia.
2004-01-27 Michael Snyder <msnyder@redhat.com>
* gencode.c: Comment and whitespace clean-ups.
Index: gencode.c
===================================================================
RCS file: /cvs/src/src/sim/sh/gencode.c,v
retrieving revision 1.24
diff -p -r1.24 gencode.c
*** gencode.c 10 Jan 2004 00:43:28 -0000 1.24
--- gencode.c 27 Jan 2004 23:12:44 -0000
***************
*** 4,10 ****
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
! This file is part of SH sim
THIS SOFTWARE IS NOT COPYRIGHTED
--- 4,10 ----
Written by Steve Chamberlain of Cygnus Support.
sac@cygnus.com
! This file is part of SH sim.
THIS SOFTWARE IS NOT COPYRIGHTED
***************
*** 20,26 ****
*/
/* This program generates the opcode table for the assembler and
! the simulator code
-t prints a pretty table for the assembler manual
-s generates the simulator code jump table
--- 20,26 ----
*/
/* This program generates the opcode table for the assembler and
! the simulator code.
-t prints a pretty table for the assembler manual
-s generates the simulator code jump table
*************** op tab[] =
*** 287,293 ****
/* sh2e */
{ "", "", "fdiv <FREG_M>,<FREG_N>", "1111nnnnmmmm0011",
"FP_OP (n, /, m);",
! "/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh4 */
--- 287,293 ----
/* sh2e */
{ "", "", "fdiv <FREG_M>,<FREG_N>", "1111nnnnmmmm0011",
"FP_OP (n, /, m);",
! "/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh4 */
*************** op tab[] =
*** 309,321 ****
/* sh2e */
{ "", "", "fldi0 <FREG_N>", "1111nnnn10001101",
"SET_FR (n, (float) 0.0);",
! "/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh2e */
{ "", "", "fldi1 <FREG_N>", "1111nnnn10011101",
"SET_FR (n, (float) 1.0);",
! "/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh2e */
--- 309,321 ----
/* sh2e */
{ "", "", "fldi0 <FREG_N>", "1111nnnn10001101",
"SET_FR (n, (float) 0.0);",
! "/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh2e */
{ "", "", "fldi1 <FREG_N>", "1111nnnn10011101",
"SET_FR (n, (float) 1.0);",
! "/* FIXME: check for DP and (n & 1) == 0? */",
},
/* sh2e */
*************** op tab[] =
*** 443,449 ****
"}",
},
! /* sh4: See fmov instructions above for move to/from extended fp registers */
/* sh2e */
{ "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010",
--- 443,450 ----
"}",
},
! /* sh4:
! See fmov instructions above for move to/from extended fp registers. */
/* sh2e */
{ "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010",
*************** op tab[] =
*** 662,672 ****
},
{ "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
! "macl (&R0,memory,n,m);",
},
{ "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
! "macw (&R0,memory,n,m,endianw);",
},
{ "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....",
--- 663,673 ----
},
{ "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
! "macl (&R0, memory, n, m);",
},
{ "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
! "macw (&R0, memory, n, m, endianw);",
},
{ "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....",
*************** op tab[] =
*** 1192,1198 ****
{ "0", "", "trapa #<imm>", "11000011i8*1....",
"long imm = 0xff & i;",
"if (i < 20 || i == 33 || i == 34 || i == 0xc3)",
! " nip += trap (i, R, PC, memory, maskl, maskw,endianw);",
#if 0
"else {",
/* SH-[12] */
--- 1193,1199 ----
{ "0", "", "trapa #<imm>", "11000011i8*1....",
"long imm = 0xff & i;",
"if (i < 20 || i == 33 || i == 34 || i == 0xc3)",
! " nip += trap (i, R, PC, memory, maskl, maskw, endianw);",
#if 0
"else {",
/* SH-[12] */
*************** op tab[] =
*** 1242,1251 ****
#if 0
{ "divs.l <REG_M>,<REG_N>", "0100nnnnmmmm1110",
! "divl (0,R[n],R[m]);",
},
{ "divu.l <REG_M>,<REG_N>", "0100nnnnmmmm1101",
! "divl (0,R[n],R[m]);",
},
#endif
--- 1243,1252 ----
#if 0
{ "divs.l <REG_M>,<REG_N>", "0100nnnnmmmm1110",
! "divl (0, R[n], R[m]);",
},
{ "divu.l <REG_M>,<REG_N>", "0100nnnnmmmm1101",
! "divl (0, R[n], R[m]);",
},
#endif
*************** gengastab ()
*** 2262,2269 ****
{
printf ("%s %-30s\n", p->code, p->name);
}
-
-
}
static unsigned char table[1 << 16];
--- 2263,2268 ----
*************** expand_opcode (val, i, s)
*** 2395,2401 ****
}
/* Print the jump table used to index an opcode into a switch
! statement entry. */
static void
dumptable (name, size, start)
--- 2394,2400 ----
}
/* Print the jump table used to index an opcode into a switch
! statement entry. */
static void
dumptable (name, size, start)
*************** gensim_caselist (p)
*** 2643,2649 ****
printf (" TL (n);\n");
{
! /* Do the refs */
char *r;
for (r = p->refs; *r; r++)
{
--- 2642,2648 ----
printf (" TL (n);\n");
{
! /* Do the refs. */
char *r;
for (r = p->refs; *r; r++)
{
*************** gensim_caselist (p)
*** 2666,2672 ****
printf (" }\n");
{
! /* Do the defs */
char *r;
for (r = p->defs; *r; r++)
{
--- 2665,2671 ----
printf (" }\n");
{
! /* Do the defs. */
char *r;
for (r = p->defs; *r; r++)
{
*************** main (ac, av)
*** 2975,2986 ****
int ac;
char **av;
{
! /* verify the table before anything else */
{
op *p;
for (p = tab; p->name; p++)
{
! /* check that the code field contains 16 bits */
if (strlen (p->code) != 16)
{
fprintf (stderr, "Code `%s' length wrong (%d) for `%s'\n",
--- 2974,2985 ----
int ac;
char **av;
{
! /* Verify the table before anything else. */
{
op *p;
for (p = tab; p->name; p++)
{
! /* Check that the code field contains 16 bits. */
if (strlen (p->code) != 16)
{
fprintf (stderr, "Code `%s' length wrong (%d) for `%s'\n",
*************** main (ac, av)
*** 2990,2996 ****
}
}
! /* now generate the requested data */
if (ac > 1)
{
if (strcmp (av[1], "-t") == 0)
--- 2989,2995 ----
}
}
! /* Now generate the requested data. */
if (ac > 1)
{
if (strcmp (av[1], "-t") == 0)