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ARM SIM: Ignore SWIs with a reason code of -1


Hi Guys,

  I am applying the patch below to allow the ARM simulator to ignore a
  SWI with a reason code of -1.  It has been discovered that this can
  happen when GDB attempts to resume an interrupted system call.  For
  an example of this see the interrupt.exp tests in the GDB testsuite.

Cheers
        Nick

2002-08-15  Nick Clifton  <nickc@redhat.com>

	* armos.c (ARMul_OSHandleSWI): Catch and ignore SWIs of -1, they
	can be caused by an interrupted system call being resumed by GDB.

Index: sim/arm/armos.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armos.c,v
retrieving revision 1.16
diff -c -3 -p -w -r1.16 armos.c
*** sim/arm/armos.c	9 Jun 2002 15:45:44 -0000	1.16
--- sim/arm/armos.c	15 Aug 2002 14:26:00 -0000
*************** ARMul_OSHandleSWI (ARMul_State * state, 
*** 553,558 ****
--- 553,565 ----
  	  /* R0 is a reason code.  */
  	  switch (state->Reg[0])
  	    {
+ 	    case -1:
+ 	      /* This can happen when a SWI is interrupted (eg receiving a
+ 		 ctrl-C whilst processing SWIRead()).  The SWI will complete
+ 		 returning -1 in r0 to the caller.  If GDB is then used to
+ 		 resume the system call the reason code will now be -1.  */
+ 	      return FALSE;
+ 	  
  	      /* Unimplemented reason codes.  */
  	    case AngelSWI_Reason_ReadC:
  	    case AngelSWI_Reason_IsTTY:
*************** ARMul_OSHandleSWI (ARMul_State * state, 
*** 685,690 ****
--- 692,704 ----
        /* These are used by the FPE code.  */
        break;
        
+     case -1:
+       /* This can happen when a SWI is interrupted (eg receiving a
+ 	 ctrl-C whilst processing SWIRead()).  The SWI will complete
+ 	 returning -1 in r0 to the caller.  If GDB is then used to
+ 	 resume the system call the reason code will now be -1.  */
+       return FALSE;
+ 	  
      case 0x180001: /* RedBoot's Syscall SWI in ARM mode.  */
        if (swi_mask & SWI_MASK_REDBOOT)
  	{


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