This is the mail archive of the
gdb-patches@sources.redhat.com
mailing list for the GDB project.
[RFC/RFA] Mutliarch h8300 step 3
- From: Andrew Volkov <Andrew dot Volkov at transas dot com>
- To: gdb-patches at sources dot redhat dot com
- Cc: ezannoni at redhat dot com, Andrew Cagney <ac131313 at cygnus dot com>
- Date: Tue, 6 Aug 2002 22:34:29 +0400
- Subject: [RFC/RFA] Mutliarch h8300 step 3
Patc for sim part:
2002-08-06 Andrey Volkov <avolkov@transas.com>
* insn.h: Remove deprecated definitions of #define DEBUG,
regnums and define all registers as vector.
* compile.c: Add additional operand type (OP_ABS_ADDR)
and remove unnecessary R_ZERO. Change RXX to SIM_H830_XXXX
Index: compile.c
===================================================================
RCS file: /cvs/src/src/sim/h8300/compile.c,v
retrieving revision 1.17
diff -u -r1.17 compile.c
--- compile.c 29 Jul 2002 17:01:57 -0000 1.17
+++ compile.c 6 Aug 2002 16:41:03 -0000
@@ -69,6 +69,7 @@
#define OP_IMM 8
#define OP_ABS 10
#define OP_EXR 11
+#define OP_ABS_ADDR 12
#define h8_opcodes ops
#define DEFINE_TABLE
#include "opcode/h8300.h"
@@ -83,26 +84,26 @@
#define HIGH_BYTE(x) (((x) >> 8) & 0xff)
#define P(X,Y) ((X << 8) | Y)
-#define BUILDSR() cpu.ccr = (I << 7) | (UI << 6)| (H<<5) | (U<<4) | \
+#define BUILDSR() cpu.regs[SIM_H8300_CCR_REGNUM] = (I << 7) | (UI << 6)|
(H<<5) | (U<<4) | \
(N << 3) | (Z << 2) | (V<<1) | C;
#define BUILDEXR() \
- if (h8300smode) cpu.exr = (trace<<7) | intMask;
+ if (h8300smode) cpu.regs[SIM_H8300_EXR_REGNUM] = (trace<<7) | intMask;
#define GETSR() \
- c = (cpu.ccr >> 0) & 1;\
- v = (cpu.ccr >> 1) & 1;\
- nz = !((cpu.ccr >> 2) & 1);\
- n = (cpu.ccr >> 3) & 1;\
- u = (cpu.ccr >> 4) & 1;\
- h = (cpu.ccr >> 5) & 1;\
- ui = ((cpu.ccr >> 6) & 1);\
- intMaskBit = (cpu.ccr >> 7) & 1;
+ c = (cpu.regs[SIM_H8300_CCR_REGNUM] >> 0) & 1;\
+ v = (cpu.regs[SIM_H8300_CCR_REGNUM] >> 1) & 1;\
+ nz = !((cpu.regs[SIM_H8300_CCR_REGNUM] >> 2) & 1);\
+ n = (cpu.regs[SIM_H8300_CCR_REGNUM] >> 3) & 1;\
+ u = (cpu.regs[SIM_H8300_CCR_REGNUM] >> 4) & 1;\
+ h = (cpu.regs[SIM_H8300_CCR_REGNUM] >> 5) & 1;\
+ ui = ((cpu.regs[SIM_H8300_CCR_REGNUM] >> 6) & 1);\
+ intMaskBit = (cpu.regs[SIM_H8300_CCR_REGNUM] >> 7) & 1;
#define GETEXR() \
if (h8300smode) { \
- trace = (cpu.exr >> 7) & 1;\
- intMask = cpu.exr & 7; }
+ trace = (cpu.regs[SIM_H8300_EXR_REGNUM] >> 7) & 1;\
+ intMask = cpu.regs[SIM_H8300_EXR_REGNUM] & 7; }
#ifdef __CHAR_IS_SIGNED__
#define SEXTCHAR(x) ((char) (x))
@@ -126,7 +127,7 @@
static int
get_now ()
{
- return time (0); /* WinXX HAS UNIX like 'time', so why not using it?
*/
+ return time (0);
}
static int
@@ -156,18 +157,14 @@
{
switch (x / 4)
{
- case OP_DISP:
- if (rn == 8)
- {
+ case OP_ABS_ADDR:
return X (OP_IMM, SP);
- }
+ case OP_DISP:
return X (OP_REG, SP);
-
case OP_MEM:
return X (OP_MEM, SP);
-
default:
- abort (); /* ?? May be something more usefull? */
+ abort (); /* ?? May be something more usefull?
*/
}
}
@@ -230,8 +227,8 @@
if (looking_for & DBIT)
{
/* Exclude adds/subs by looking at bit 0 and 2, and
- make sure the operand size, either w or l,
- matches by looking at bit 1. */
+ make sure the operand size, either w or l,
+ matches by looking at bit 1. */
if ((looking_for & 7) != (thisnib & 7))
goto fail;
@@ -272,8 +269,7 @@
abs = (data[i] << 24)
| (data[i + 1] << 16)
- | (data[i + 2] << 8)
- | (data[i + 3]);
+ | (data[i + 2] << 8) | (data[i + 3]);
plen = 32;
}
@@ -391,9 +387,8 @@
}
else if (x & (ABS | ABSJMP | ABS8MEM))
{
- p->type = X (OP_DISP, size);
+ p->type = X (OP_ABS_ADDR, size);
p->literal = abs;
- p->reg = 8;
}
else if (x & MEMIND)
{
@@ -436,8 +431,7 @@
/* But a jmp or a jsr gets automagically lvalued,
since we branch to their address not their
contents. */
- if (q->how == O (O_JSR, SB)
- || q->how == O (O_JMP, SB))
+ if (q->how == O (O_JSR, SB) || q->how == O (O_JMP, SB))
{
dst->src.type = lvalue (dst->src.type, dst->src.reg);
}
@@ -492,6 +486,7 @@
cpu.cache_top = idx;
/* Throw away its old meaning. */
+
cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
/* Set to new address. */
@@ -613,6 +608,21 @@
t &= cpu.mask;
return GET_MEMORY_L (t);
+ case X (OP_ABS_ADDR, SB):
+ t = abs;
+ t &= cpu.mask;
+ return GET_MEMORY_B (t);
+
+ case X (OP_ABS_ADDR, SW):
+ t = abs;
+ t &= cpu.mask;
+ return GET_MEMORY_W (t);
+
+ case X (OP_ABS_ADDR, SL):
+ t = abs;
+ t &= cpu.mask;
+ return GET_MEMORY_L (t);
+
case X (OP_MEM, SL):
t = GET_MEMORY_L (abs);
t &= cpu.mask;
@@ -623,8 +633,13 @@
t &= cpu.mask;
return t;
+ case X (OP_MEM, SB):
+ t = GET_MEMORY_B (abs);
+ t &= cpu.mask;
+ return t;
+
default:
- abort (); /* ?? May be something more usefull? */
+ abort (); /* ?? May be something more usefull?
*/
}
}
@@ -687,6 +702,25 @@
t &= cpu.mask;
SET_MEMORY_L (t, n);
break;
+
+ case X (OP_ABS_ADDR, SB):
+ t = abs;
+ t &= cpu.mask;
+ SET_MEMORY_B (t, n);
+ break;
+
+ case X (OP_ABS_ADDR, SW):
+ t = abs;
+ t &= cpu.mask;
+ SET_MEMORY_W (t, n);
+ break;
+
+ case X (OP_ABS_ADDR, SL):
+ t = abs;
+ t &= cpu.mask;
+ SET_MEMORY_L (t, n);
+ break;
+
default:
abort ();
}
@@ -697,10 +731,10 @@
{
short int i;
struct
- {
- char low;
- char high;
- }
+ {
+ char low;
+ char high;
+ }
u;
}
@@ -733,12 +767,17 @@
abort ();
cpu.mask = memory_size - 1;
- for (i = 0; i < 9; i++)
+ for (i = 0; i <= SIM_H8300_R7_REGNUM; i++)
{
cpu.regs[i] = 0;
}
- for (i = 0; i < 8; i++)
+ cpu.cycles = 0;
+ cpu.ticks = 0;
+ cpu.insts = 0;
+ cpu.compiles = 0;
+
+ for (i = 0; i <= SIM_H8300_R7_REGNUM; i++)
{
unsigned char *p = (unsigned char *) (cpu.regs + i);
unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
@@ -772,9 +811,6 @@
cpu.regs[i] = 0;
lreg[i] = &cpu.regs[i];
}
-
- lreg[8] = &cpu.regs[8];
-
/* Initialize the seg registers. */
if (!cpu.cache)
sim_set_simcache_size (CSIZE);
@@ -943,28 +979,6 @@
return 1;
}
-#define R0_REGNUM 0
-#define R1_REGNUM 1
-#define R2_REGNUM 2
-#define R3_REGNUM 3
-#define R4_REGNUM 4
-#define R5_REGNUM 5
-#define R6_REGNUM 6
-#define R7_REGNUM 7
-
-#define SP_REGNUM R7_REGNUM /* Contains address of top of stack
*/
-#define FP_REGNUM R6_REGNUM /* Contains address of executing
- * stack frame */
-
-#define CCR_REGNUM 8 /* Contains processor status */
-#define PC_REGNUM 9 /* Contains program counter */
-
-#define CYCLE_REGNUM 10
-
-#define EXR_REGNUM 11
-#define INST_REGNUM 12
-#define TICK_REGNUM 13
-
void
sim_resume (sd, step, siggnal)
SIM_DESC sd;
@@ -999,7 +1013,7 @@
cpu.exception = 0;
}
- pc = cpu.pc;
+ pc = cpu.regs[SIM_H8300_PC_REGNUM];
/* The PC should never be odd. */
if (pc & 0x1)
@@ -1079,13 +1093,8 @@
#define EA ea = fetch (&code->src);
#define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst);
- ALUOP (1, O_SUB, RD_EA;
- ea = -ea;
- res = rd + ea);
- ALUOP (1, O_NEG, EA;
- ea = -ea;
- rd = 0;
- res = rd + ea);
+ ALUOP (1, O_SUB, RD_EA; ea = -ea; res = rd + ea);
+ ALUOP (1, O_NEG, EA; ea = -ea; rd = 0; res = rd + ea);
case O (O_ADD, SB):
rd = GET_B_REG (code->dst.reg);
@@ -1104,14 +1113,11 @@
goto alu32;
- LOGOP (O_AND, RD_EA;
- res = rd & ea);
+ LOGOP (O_AND, RD_EA; res = rd & ea);
- LOGOP (O_OR, RD_EA;
- res = rd | ea);
+ LOGOP (O_OR, RD_EA; res = rd | ea);
- LOGOP (O_XOR, RD_EA;
- res = rd ^ ea);
+ LOGOP (O_XOR, RD_EA; res = rd ^ ea);
case O (O_MOV_TO_MEM, SB):
@@ -1140,47 +1146,54 @@
case O (O_EEPMOV, SB):
case O (O_EEPMOV, SW):
- if (h8300hmode||h8300smode)
+ if (h8300hmode || h8300smode)
{
- register unsigned char *_src,*_dst;
- unsigned int count = (code->opcode == O(O_EEPMOV,
SW))?cpu.regs[R4_REGNUM]&0xffff:
- cpu.regs[R4_REGNUM]&0xff;
-
- _src = cpu.regs[R5_REGNUM] < memory_size ?
cpu.memory+cpu.regs[R5_REGNUM] :
- cpu.eightbit + (cpu.regs[R5_REGNUM] & 0xff);
- if ((_src+count)>=(cpu.memory+memory_size))
+ register unsigned char *src, *dst;
+ unsigned int count =
+ (code->opcode ==
+ O (O_EEPMOV,
+ SW)) ? cpu.regs[SIM_H8300_R4_REGNUM] & 0xffff : cpu.
+ regs[SIM_H8300_R4_REGNUM] & 0xff;
+
+ src = cpu.regs[SIM_H8300_R5_REGNUM] < memory_size ?
+ cpu.memory + cpu.regs[SIM_H8300_R5_REGNUM] :
+ cpu.eightbit + (cpu.regs[SIM_H8300_R5_REGNUM] & 0xff);
+
+ if ((src + count) >= (cpu.memory + memory_size))
{
- if ((_src+count)>=(cpu.eightbit+0x100))
+ if ((src + count) >= (cpu.eightbit + 0x100))
goto illegal;
}
- _dst = cpu.regs[R6_REGNUM] < memory_size ?
cpu.memory+cpu.regs[R6_REGNUM] :
- cpu.eightbit +
(cpu.regs[R6_REGNUM] & 0xff);
- if ((_dst+count)>=(cpu.memory+memory_size))
+
+ dst = cpu.regs[SIM_H8300_R6_REGNUM] < memory_size ?
+ cpu.memory + cpu.regs[SIM_H8300_R6_REGNUM] :
+ cpu.eightbit + (cpu.regs[SIM_H8300_R6_REGNUM] & 0xff);
+
+ if ((dst + count) >= (cpu.memory + memory_size))
{
- if ((_dst+count)>=(cpu.eightbit+0x100))
+ if ((dst + count) >= (cpu.eightbit + 0x100))
goto illegal;
}
- memcpy(_dst,_src,count);
+ memcpy (dst, src, count);
- cpu.regs[R5_REGNUM]+=count;
- cpu.regs[R6_REGNUM]+=count;
- cpu.regs[R4_REGNUM]&=(code->opcode == O(O_EEPMOV,
SW))?(~0xffff):(~0xff);
- cycles += 2*count;
+ cpu.regs[SIM_H8300_R5_REGNUM] += count;
+ cpu.regs[SIM_H8300_R6_REGNUM] += count;
+ cpu.regs[SIM_H8300_R4_REGNUM] &= (code->opcode == O (O_EEPMOV,
SW)) ?
+ (~0xffff) : (~0xff);
+ cycles += 2 * count;
goto next;
}
goto illegal;
case O (O_ADDS, SL):
SET_L_REG (code->dst.reg,
- GET_L_REG (code->dst.reg)
- + code->src.literal);
+ GET_L_REG (code->dst.reg) + code->src.literal);
goto next;
case O (O_SUBS, SL):
SET_L_REG (code->dst.reg,
- GET_L_REG (code->dst.reg)
- - code->src.literal);
+ GET_L_REG (code->dst.reg) - code->src.literal);
goto next;
case O (O_CMP, SB):
@@ -1248,8 +1261,8 @@
SET_L_REG (code->dst.reg, res);
goto just_flags_inc32;
-#define GET_CCR(x) BUILDSR();x = cpu.ccr
-#define GET_EXR(x) BUILDEXR ();x = cpu.exr
+#define GET_CCR(x) BUILDSR();x = cpu.regs[SIM_H8300_CCR_REGNUM]
+#define GET_EXR(x) BUILDEXR ();x = cpu.regs[SIM_H8300_EXR_REGNUM]
case O (O_LDC, SB):
case O (O_LDC, SW):
@@ -1394,36 +1407,74 @@
case O (O_SYSCALL, SB):
{
- char c = cpu.regs[2];
+ char c = cpu.regs[SIM_H8300_R3_REGNUM];
sim_callback->write_stdout (sim_callback, &c, 1);
}
goto next;
- ONOT (O_NOT, rd = ~rd; v = 0;);
- OSHIFTS (O_SHLL,
- c = rd & hm; v = 0; rd <<= 1,
- c = rd & (hm >> 1); v = 0; rd <<= 2);
- OSHIFTS (O_SHLR,
- c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
- c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
- OSHIFTS (O_SHAL,
- c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd
<<= 1,
- c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >>
2)) << 2); rd <<= 2);
- OSHIFTS (O_SHAR,
- t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
- t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >>
1);
- OSHIFTS (O_ROTL,
- c = rd & hm; v = 0; rd <<= 1; rd |= C,
- c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd
<<= 1; rd |= C);
- OSHIFTS (O_ROTR,
- c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd
|= hm,
- c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd
|= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
- OSHIFTS (O_ROTXL,
- t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
- t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd &
hm; rd <<= 1; rd |= C; c = t);
- OSHIFTS (O_ROTXR,
- t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm;
c = t; v = 0,
- t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm;
c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c =
t);
+ ONOT (O_NOT, rd = ~rd;
+ v = 0;
+ );
+ OSHIFTS (O_SHLL, c = rd & hm;
+ v = 0;
+ rd <<= 1, c = rd & (hm >> 1);
+ v = 0;
+ rd <<= 2);
+ OSHIFTS (O_SHLR, c = rd & 1;
+ v = 0;
+ rd = (unsigned int) rd >> 1, c = rd & 2;
+ v = 0;
+ rd = (unsigned int) rd >> 2);
+ OSHIFTS (O_SHAL, c = rd & hm;
+ v = (rd & hm) != ((rd & (hm >> 1)) << 1);
+ rd <<= 1, c = rd & (hm >> 1);
+ v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2);
+ rd <<= 2);
+ OSHIFTS (O_SHAR, t = rd & hm;
+ c = rd & 1;
+ v = 0;
+ rd >>= 1;
+ rd |= t, t = rd & hm;
+ c = rd & 2;
+ v = 0;
+ rd >>= 2;
+ rd |= t | t >> 1);
+ OSHIFTS (O_ROTL, c = rd & hm;
+ v = 0;
+ rd <<= 1;
+ rd |= C, c = rd & hm;
+ v = 0;
+ rd <<= 1;
+ rd |= C;
+ c = rd & hm;
+ rd <<= 1;
+ rd |= C);
+ OSHIFTS (O_ROTR, c = rd & 1;
+ v = 0;
+ rd = (unsigned int) rd >> 1;
+ if (c) rd |= hm,
+ c = rd & 1; v = 0; rd = (unsigned int) rd >> 1;
+ if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1;
+ if (c) rd |= hm);
+ OSHIFTS (O_ROTXL, t = rd & hm;
+ rd <<= 1;
+ rd |= C;
+ c = t;
+ v = 0, t = rd & hm;
+ rd <<= 1;
+ rd |= C;
+ c = t;
+ v = 0;
+ t = rd & hm;
+ rd <<= 1;
+ rd |= C;
+ c = t);
+ OSHIFTS (O_ROTXR, t = rd & 1;
+ rd = (unsigned int) rd >> 1;
+ if (C) rd |= hm; c = t; v = 0,
+ t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm;
+ c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1;
+ if (C) rd |= hm; c = t);
case O (O_JMP, SB):
{
@@ -1437,7 +1488,7 @@
int tmp;
pc = fetch (&code->src);
call:
- tmp = cpu.regs[7];
+ tmp = cpu.regs[SIM_H8300_R7_REGNUM];
if (h8300hmode)
{
@@ -1449,7 +1500,7 @@
tmp -= 2;
SET_MEMORY_W (tmp, code->next_pc);
}
- cpu.regs[7] = tmp;
+ cpu.regs[SIM_H8300_R7_REGNUM] = tmp;
goto end;
}
@@ -1461,7 +1512,7 @@
{
int tmp;
- tmp = cpu.regs[7];
+ tmp = cpu.regs[SIM_H8300_R7_REGNUM];
if (h8300hmode)
{
@@ -1474,7 +1525,7 @@
tmp += 2;
}
- cpu.regs[7] = tmp;
+ cpu.regs[SIM_H8300_R7_REGNUM] = tmp;
goto end;
}
@@ -1487,10 +1538,11 @@
contains just the right (er, wrong) value? */
cpu.state = SIM_STATE_STOPPED;
/* The format of r0 is defined by target newlib. Expand
- the macros here instead of looking for .../sys/wait.h. */
+ the macros here instead of looking for .../sys/wait.h. */
#define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
#define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
- if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED
(cpu.regs[0]))
+ if (!SIM_WIFEXITED (cpu.regs[SIM_H8300_R0_REGNUM])
+ && SIM_WIFSIGNALED (cpu.regs[SIM_H8300_R0_REGNUM]))
cpu.exception = SIGILL;
else
cpu.exception = SIGTRAP;
@@ -1506,10 +1558,8 @@
OBITOP (O_BSET, 1, 1, ea |= m);
OBITOP (O_BLD, 1, 0, c = ea & m);
OBITOP (O_BILD, 1, 0, c = !(ea & m));
- OBITOP (O_BST, 1, 1, ea &= ~m;
- if (C) ea |= m);
- OBITOP (O_BIST, 1, 1, ea &= ~m;
- if (!C) ea |= m);
+ OBITOP (O_BST, 1, 1, ea &= ~m; if (C) ea |= m);
+ OBITOP (O_BIST, 1, 1, ea &= ~m; if (!C) ea |= m);
OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
@@ -1539,16 +1589,16 @@
goto illegal;
switch (code->src.reg)
{
- case R0_REGNUM:
- case R1_REGNUM:
- case R4_REGNUM:
- case R5_REGNUM:
+ case SIM_H8300_R0_REGNUM:
+ case SIM_H8300_R1_REGNUM:
+ case SIM_H8300_R4_REGNUM:
+ case SIM_H8300_R5_REGNUM:
break;
default:
goto illegal;
}
res = fetch (&code->src);
- store (&code->src,res|0x80);
+ store (&code->src, res | 0x80);
goto just_flags_log8;
case O (O_DIVU, SB):
@@ -1615,7 +1665,7 @@
goto next;
}
case O (O_EXTS, SW):
- rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst.
*/
+ rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not
dst. */
ea = rd & 0x80 ? -256 : 0;
res = rd + ea;
goto log16;
@@ -1649,8 +1699,8 @@
firstreg &= 0xf;
for (i = firstreg; i <= firstreg + nregs; i++)
{
- cpu.regs[7] -= 4;
- SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
+ cpu.regs[SIM_H8300_R7_REGNUM] -= 4;
+ SET_MEMORY_L (cpu.regs[SIM_H8300_R7_REGNUM], cpu.regs[i]);
}
}
goto next;
@@ -1666,14 +1716,14 @@
firstreg &= 0xf;
for (i = firstreg; i >= firstreg - nregs; i--)
{
- cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
- cpu.regs[7] += 4;
+ cpu.regs[i] = GET_MEMORY_L (cpu.regs[SIM_H8300_R7_REGNUM]);
+ cpu.regs[SIM_H8300_R7_REGNUM] += 4;
}
}
goto next;
default:
- illegal:
+ illegal:
cpu.state = SIM_STATE_STOPPED;
cpu.exception = SIGILL;
goto end;
@@ -1684,12 +1734,12 @@
setc:
if (code->dst.type == OP_CCR)
{
- cpu.ccr = res;
+ cpu.regs[SIM_H8300_CCR_REGNUM] = res;
GETSR ();
}
else if (code->dst.type == OP_EXR && h8300smode)
{
- cpu.exr = res;
+ cpu.regs[SIM_H8300_EXR_REGNUM] = res;
GETEXR ();
}
else
@@ -1786,13 +1836,11 @@
switch (code->opcode / 4)
{
case O_ADD:
- v = ((rd & 0x80) == (ea & 0x80)
- && (rd & 0x80) != (res & 0x80));
+ v = ((rd & 0x80) == (ea & 0x80) && (rd & 0x80) != (res & 0x80));
break;
case O_SUB:
case O_CMP:
- v = ((rd & 0x80) != (-ea & 0x80)
- && (rd & 0x80) != (res & 0x80));
+ v = ((rd & 0x80) != (-ea & 0x80) && (rd & 0x80) != (res & 0x80));
break;
case O_NEG:
v = (rd == 0x80);
@@ -1833,7 +1881,8 @@
case O_ADD:
v = ((rd & 0x80000000) == (ea & 0x80000000)
&& (rd & 0x80000000) != (res & 0x80000000));
- c = ((unsigned) res < (unsigned) rd) || ((unsigned) res <
(unsigned) ea);
+ c = ((unsigned) res < (unsigned) rd)
+ || ((unsigned) res < (unsigned) ea);
break;
case O_SUB:
case O_CMP:
@@ -1853,10 +1902,6 @@
end:
;
-#if 0
- if (cpu.regs[8])
- abort ();
-#endif
if (--poll_count < 0)
{
@@ -1872,7 +1917,7 @@
cpu.cycles += cycles;
cpu.insts += insts;
- cpu.pc = pc;
+ cpu.regs[SIM_H8300_PC_REGNUM] = pc;
BUILDSR ();
BUILDEXR ();
cpu.mask = oldmask;
@@ -1895,7 +1940,6 @@
int size;
{
int i;
-
init_pointers ();
if (addr < 0)
return 0;
@@ -1905,11 +1949,13 @@
{
cpu.memory[addr + i] = buffer[i];
cpu.cache_idx[addr + i] = 0;
+
}
else
cpu.eightbit[(addr + i) & 0xff] = buffer[i];
}
return size;
+
}
int
@@ -1947,36 +1993,36 @@
init_pointers ();
switch (rn)
{
- case PC_REGNUM:
- cpu.pc = intval;
+ case SIM_H8300_PC_REGNUM:
+ cpu.regs[SIM_H8300_PC_REGNUM] = intval;
break;
default:
abort ();
- case R0_REGNUM:
- case R1_REGNUM:
- case R2_REGNUM:
- case R3_REGNUM:
- case R4_REGNUM:
- case R5_REGNUM:
- case R6_REGNUM:
- case R7_REGNUM:
+ case SIM_H8300_R0_REGNUM:
+ case SIM_H8300_R1_REGNUM:
+ case SIM_H8300_R2_REGNUM:
+ case SIM_H8300_R3_REGNUM:
+ case SIM_H8300_R4_REGNUM:
+ case SIM_H8300_R5_REGNUM:
+ case SIM_H8300_R6_REGNUM:
+ case SIM_H8300_R7_REGNUM:
cpu.regs[rn] = intval;
break;
- case CCR_REGNUM:
- cpu.ccr = intval;
+ case SIM_H8300_CCR_REGNUM:
+ cpu.regs[SIM_H8300_CCR_REGNUM] = intval;
break;
- case EXR_REGNUM:
- cpu.exr = intval;
+ case SIM_H8300_EXR_REGNUM:
+ cpu.regs[SIM_H8300_EXR_REGNUM] = intval;
break;
- case CYCLE_REGNUM:
+ case SIM_H8300_CYCLE_REGNUM:
cpu.cycles = longval;
break;
- case INST_REGNUM:
+ case SIM_H8300_INST_REGNUM:
cpu.insts = longval;
break;
- case TICK_REGNUM:
+ case SIM_H8300_TICK_REGNUM:
cpu.ticks = longval;
break;
}
@@ -1990,62 +2036,75 @@
unsigned char *buf;
int length;
{
- int v;
+ int v, size;
int longreg = 0;
+ int control_reg = 0;
init_pointers ();
- if (!h8300smode && rn >=EXR_REGNUM)
- rn++;
switch (rn)
{
default:
abort ();
- case CCR_REGNUM:
- v = cpu.ccr;
+ case SIM_H8300_CCR_REGNUM:
+ v = cpu.regs[rn];
+ control_reg = 1;
break;
- case EXR_REGNUM:
- v = cpu.exr;
+ case SIM_H8300_EXR_REGNUM:
+ v = cpu.regs[rn];
+ control_reg = 1;
break;
- case PC_REGNUM:
- v = cpu.pc;
+ case SIM_H8300_PC_REGNUM:
+ v = cpu.regs[rn];
break;
- case R0_REGNUM:
- case R1_REGNUM:
- case R2_REGNUM:
- case R3_REGNUM:
- case R4_REGNUM:
- case R5_REGNUM:
- case R6_REGNUM:
- case R7_REGNUM:
+ case SIM_H8300_R0_REGNUM:
+ case SIM_H8300_R1_REGNUM:
+ case SIM_H8300_R2_REGNUM:
+ case SIM_H8300_R3_REGNUM:
+ case SIM_H8300_R4_REGNUM:
+ case SIM_H8300_R5_REGNUM:
+ case SIM_H8300_R6_REGNUM:
+ case SIM_H8300_R7_REGNUM:
v = cpu.regs[rn];
break;
- case CYCLE_REGNUM:
+ case SIM_H8300_CYCLE_REGNUM:
v = cpu.cycles;
longreg = 1;
break;
- case TICK_REGNUM:
+ case SIM_H8300_TICK_REGNUM:
v = cpu.ticks;
longreg = 1;
break;
- case INST_REGNUM:
+ case SIM_H8300_INST_REGNUM:
v = cpu.insts;
longreg = 1;
break;
}
+
+#if 0 /* FIXME: This should work but we can't use
it. */
+ if (control_reg)
+ {
+ buf[0] = v;
+ size = 1;
+ }
+
+ else
+#endif
if (h8300hmode || longreg)
{
buf[0] = v >> 24;
buf[1] = v >> 16;
buf[2] = v >> 8;
buf[3] = v >> 0;
+ size = 4;
}
else
{
buf[0] = v >> 8;
buf[1] = v;
+ size = 2;
}
- return -1;
+ return size;
}
void
@@ -2054,14 +2113,21 @@
enum sim_stop *reason;
int *sigrc;
{
-#if 0 /* FIXME: This should work but we can't use it.
- grep for SLEEP above. */
+#if 0 /* FIXME: This should work but we can't use
it.
+ grep for SLEEP above. */
switch (cpu.state)
{
- case SIM_STATE_EXITED : *reason = sim_exited; break;
- case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
- case SIM_STATE_STOPPED : *reason = sim_stopped; break;
- default : abort ();
+ case SIM_STATE_EXITED:
+ *reason = sim_exited;
+ break;
+ case SIM_STATE_SIGNALLED:
+ *reason = sim_signalled;
+ break;
+ case SIM_STATE_STOPPED:
+ *reason = sim_stopped;
+ break;
+ default:
+ abort ();
}
#else
*reason = sim_stopped;
@@ -2164,6 +2230,14 @@
sim_kind = kind;
myname = argv[0];
sim_callback = ptr;
+
+ if (abfd != NULL)
+ {
+ unsigned long mach = bfd_get_mach (abfd);
+ set_h8300h (mach == bfd_mach_h8300h || mach == bfd_mach_h8300s,
+ mach == bfd_mach_h8300s);
+ }
+
/* Fudge our descriptor. */
return (SIM_DESC) 1;
}
@@ -2200,7 +2274,7 @@
if (prog_bfd != NULL)
{
/* Set the cpu type. We ignore failure from bfd_check_format
- and bfd_openr as sim_load_file checks too. */
+ and bfd_openr as sim_load_file checks too. */
if (bfd_check_format (prog_bfd, bfd_object))
{
unsigned long mach = bfd_get_mach (prog_bfd);
@@ -2239,7 +2313,9 @@
free (cpu.eightbit);
cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
+
cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
+
cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
/* `msize' must be a power of two. */
@@ -2248,9 +2324,7 @@
cpu.mask = memory_size - 1;
if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
- sim_kind == SIM_OPEN_DEBUG,
- 0, sim_write)
- == NULL)
+ sim_kind == SIM_OPEN_DEBUG, 0, sim_write) == NULL)
{
/* Close the bfd if we opened it. */
if (abfd == NULL && prog_bfd != NULL)
@@ -2272,9 +2346,9 @@
char **env;
{
if (abfd != NULL)
- cpu.pc = bfd_get_start_address (abfd);
+ cpu.regs[SIM_H8300_PC_REGNUM] = bfd_get_start_address (abfd);
else
- cpu.pc = 0;
+ cpu.regs[SIM_H8300_PC_REGNUM] = 0;
return SIM_RC_OK;
}
Index: inst.h
===================================================================
RCS file: /cvs/src/src/sim/h8300/inst.h,v
retrieving revision 1.3
diff -u -r1.3 inst.h
--- inst.h 17 May 2002 19:19:24 -0000 1.3
+++ inst.h 6 Aug 2002 16:41:03 -0000
@@ -1,5 +1,3 @@
-#define DEBUG
-
/* These define the size of main memory for the simulator.
Note the size of main memory for the H8/300H is only 256k. Keeping it
@@ -14,6 +12,9 @@
outside of main memory refers to the eightbit area (in theory, this
can only happen when simulating H8/300H programs). We make no attempt
to catch overlapping addresses, wrapped addresses, etc etc. */
+#ifndef __INST_H__
+#define __INST_H__
+
#define H8300_MSIZE (1<<16)
/* avolkov:
@@ -25,19 +26,6 @@
#define CSIZE 1000
-/* Local register names */
-typedef enum
-{
- R0, R1, R2, R3, R4, R5, R6, R7,
- R_ZERO,
- R_PC,
- R_CCR,
- R_EXR,
- R_HARD_0,
- R_LAST,
-} reg_type;
-
-
/* Structure used to describe addressing */
typedef struct
@@ -47,8 +35,6 @@
int literal;
} ea_type;
-
-
typedef struct
{
ea_type src;
@@ -57,24 +43,20 @@
int next_pc;
int oldpc;
int cycles;
-#ifdef DEBUG
-struct h8_opcode *op;
-#endif
+ struct h8_opcode *op;
}
decoded_inst;
enum h8300_sim_state {
- SIM_STATE_RUNNING, SIM_STATE_EXITED, SIM_STATE_SIGNALLED,
SIM_STATE_STOPPED
+ SIM_STATE_RUNNING, SIM_STATE_EXITED, SIM_STATE_SIGNALLED,
+ SIM_STATE_STOPPED
};
typedef struct
{
enum h8300_sim_state state;
int exception;
- unsigned int regs[9];
- int pc;
- int ccr;
- int exr;
+ unsigned int regs[SIM_H8300_S_NUM_REGS];
unsigned char *memory;
unsigned char *eightbit;
@@ -94,3 +76,5 @@
#endif
}
cpu_state_type;
+
+#endif /* __INST_H__ */