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[applied mips sim patch] more MIPS fpu cleanup


some more MIPS fpu cleanup ... in preparation for even more MIPS fpu
cleanup (but, next time, which actually includes some "real" changes 8-).


chris
===================================================================
2002-06-03  Chris Demetriou  <cgd@broadcom.com>

	* sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
	(Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
	file, remove PARAMS from prototypes.
	(value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
	simulator state arguments.
	(ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
	pass simulator state arguments.
	* cp1.c (SD): Redefine as CPU_STATE(cpu).
	(store_fpr, convert): Remove 'sd' argument.
	(value_fpr): Likewise.  Convert to use 'SD' instead.
 
Index: cp1.c
===================================================================
RCS file: /cvs/src/src/sim/mips/cp1.c,v
retrieving revision 1.8
diff -u -p -r1.8 cp1.c
--- cp1.c	4 Jun 2002 00:18:46 -0000	1.8
+++ cp1.c	4 Jun 2002 01:33:30 -0000
@@ -21,7 +21,7 @@
 
 /* Within cp1.c we refer to sim_cpu directly.  */
 #define CPU cpu
-#define SD sd
+#define SD CPU_STATE(cpu)
 
 /*-- FPU support routines ---------------------------------------------------*/
 
@@ -63,8 +63,7 @@ static const char *fpu_rounding_mode_nam
 #endif
 
 uword64
-value_fpr (SIM_DESC sd,
-	   sim_cpu *cpu,
+value_fpr (sim_cpu *cpu,
 	   address_word cia,
 	   int fpr,
 	   FP_formats fmt)
@@ -95,7 +94,7 @@ value_fpr (SIM_DESC sd,
     }
   if (fmt != FPR_STATE[fpr])
     {
-      sim_io_eprintf (sd, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
+      sim_io_eprintf (SD, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
 		      fpr, fpu_format_name (FPR_STATE[fpr]),
 		      fpu_format_name (fmt), pr_addr (cia));
       FPR_STATE[fpr] = fmt_unknown;
@@ -195,8 +194,7 @@ value_fpr (SIM_DESC sd,
 }
 
 void
-store_fpr (SIM_DESC sd,
-	   sim_cpu *cpu,
+store_fpr (sim_cpu *cpu,
 	   address_word cia,
 	   int fpr,
 	   FP_formats fmt,
@@ -894,8 +892,7 @@ SquareRoot (op, fmt)
 }
 
 uword64
-convert (SIM_DESC sd,
-	 sim_cpu *cpu,
+convert (sim_cpu *cpu,
 	 address_word cia,
 	 int rm,
 	 uword64 op,
Index: sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.16
diff -u -p -r1.16 sim-main.h
--- sim-main.h	4 Jun 2002 00:18:46 -0000	1.16
+++ sim-main.h	4 Jun 2002 01:33:30 -0000
@@ -80,28 +80,6 @@ typedef enum {
  fmt_uninterpreted_64 = 0x80000000U,
 } FP_formats;
 
-unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
-#define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
-
-void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
-#define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
-
-int NaN PARAMS ((unsigned64 op, FP_formats fmt));
-int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
-int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
-unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
-unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
-unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
-unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
-unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
-#define Convert(rm,op,from,to) \
-convert (SD, CPU, cia, rm, op, from, to)
-
 /* Macro to update FPSR condition-code field. This is complicated by
    the fact that there is a hole in the index range of the bits within
    the FCSR register. Also, the number of bits visible depends on the
@@ -728,6 +706,30 @@ decode_coproc (SD, CPU, cia, (instructio
 
 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
   
+
+/* FPR access.  */
+unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
+#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
+void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
+#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
+
+
+/* FPU operations.  */
+int NaN (unsigned64 op, FP_formats fmt);
+int Infinity (unsigned64 op, FP_formats fmt);
+int Less (unsigned64 op1, unsigned64 op2, FP_formats fmt);
+int Equal (unsigned64 op1, unsigned64 op2, FP_formats fmt);
+unsigned64 AbsoluteValue (unsigned64 op, FP_formats fmt);
+unsigned64 Negate (unsigned64 op, FP_formats fmt);
+unsigned64 Add (unsigned64 op1, unsigned64 op2, FP_formats fmt);
+unsigned64 Sub (unsigned64 op1, unsigned64 op2, FP_formats fmt);
+unsigned64 Multiply (unsigned64 op1, unsigned64 op2, FP_formats fmt);
+unsigned64 Divide (unsigned64 op1, unsigned64 op2, FP_formats fmt);
+unsigned64 Recip (unsigned64 op, FP_formats fmt);
+unsigned64 SquareRoot (unsigned64 op, FP_formats fmt);
+unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
+#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
+
 
 /* MDMX access.  */
 


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