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Re:[PATCH/RFA] h8300 Multiple changes to gdb/sim-stage3

Splitting after suggestions of Andrew Cagney.

Andrey Volkov

2002-05-15  Andrey Volkov  <avolkov@sources.redhat.com>
	* include/opcode/h8300.h: Corrected defs of all
			  	  control regs and eepmov instr.

diff -ruN insight-5.0.92.old/include/opcode/h8300.h
insight-5.0.92.new/include/opcode/h8300.h
--- insight-5.0.92.old/include/opcode/h8300.h	Mon Nov  5 19:04:43 2001
+++ insight-5.0.92.new/include/opcode/h8300.h	Mon Nov  5 19:08:07 2001
@@ -333,8 +333,8 @@
   NEW_SOP(O(O_AND,SL),0,6,"and.l"),{{IMM32,RD32,E
}},{{0x7,0xA,0x6,B30|RD32,IMM32LIST,E}} EOP,
   NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{{RS32,RD32,E
}},{{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E}} EOP,
 
-  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR,E}},{{
0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
-  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR,E}},{{
0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
+  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR|DST,E}},{{
0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
+  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR|DST,E}},{{
0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
 
   BITOP(O(O_BAND,SB), IMM3|B30,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
   BRANCH(O(O_BRA,SB),"bra",0x0),
@@ -391,14 +391,14 @@
   NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{{DBIT,RD16,E
}},{{0x1,0xB,0x5|DBIT,RD16,E}} EOP,
   NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{{DBIT,RD32,E
}},{{0x1,0xB,0x7|DBIT,RD32|B30,E}} EOP,
 
-  NEW_SOP(O(O_DIVU,SB),1,6,"divxu.b"), {{RS8,RD16,E}},
{{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP,
-
NEW_SOP(O(O_DIVU,SW),0,20,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32
,E}}EOP,
+  NEW_SOP(O(O_DIVU,SB),1,13,"divxu.b"), {{RS8,RD16,E}},
{{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP,
+
NEW_SOP(O(O_DIVU,SW),0,21,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32
,E}}EOP,
     
-  NEW_SOP(O(O_DIVS,SB),0,20,"divxs.b") ,{{RS8,RD16,E
}},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP,
-  NEW_SOP(O(O_DIVS,SW),0,02,"divxs.w") ,{{RS16,RD32,E
}},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP,
+  NEW_SOP(O(O_DIVS,SB),0,13,"divxs.b") ,{{RS8,RD16,E
}},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP,
+  NEW_SOP(O(O_DIVS,SW),0,21,"divxs.w") ,{{RS16,RD32,E
}},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP,
 
-
NEW_SOP(O(O_EEPMOV,SB),1,50,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,
0x8,0xF,E}}EOP,
-
NEW_SOP(O(O_EEPMOV,SW),0,50,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,
0x8,0xF,E}} EOP,
+
NEW_SOP(O(O_EEPMOV,SB),1,4,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0
x8,0xF,E}}EOP,
+
NEW_SOP(O(O_EEPMOV,SW),0,4,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0
x8,0xF,E}} EOP,
     
   NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{{OR16,E,0}},{{0x1,0x7,0xD,OR16,E
}}EOP,
   NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{{OR32,E,0}},{{0x1,0x7,0xF,OR32|B30,E
}}EOP,
@@ -419,23 +419,23 @@
 
SOP(O(O_JSR,SB),8,"jsr"),{{SRC|ABSJMP,E,0}},{{0x5,0xE,SRC|ABSJMP,IGNORE,IGNO
RE,IGNORE,IGNORE,IGNORE,E}}EOP,
 
SOP(O(O_JSR,SB),8,"jsr"),{{SRC|MEMIND,E,0}},{{0x5,0xF,SRC|MEMIND,IGNORE,E,0,
0,0,0}}EOP,
 
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR,E}},         {{
0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR,E}},          {{
0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR,E}},
{{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR,E}},
{{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP,
-
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR,E}},{{PREFIXLDC,0x6,0xF,B
30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR,E}},{{PREFIXLDC,0x7,0x8,B
30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR,E}},
{{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR,E}},
{{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP,
-
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR,E}},         {{
0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR,E}},          {{
0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR,E}},     {{
0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR,E}},     {{
0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR,E}},{{
0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR,E}},{{
0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR,E}},        {{
0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR,E}},        {{
0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP,
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR|DST,E}},         {{
0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR|DST,E}},          {{
0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR|DST,E}},
{{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR|DST,E}},
{{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP,
+
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR|DST,E}},{{PREFIXLDC,0x6,0
xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+
NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR|DST,E}},{{PREFIXLDC,0x7,0
x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR|DST,E}},
{{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR|DST,E}},
{{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP,
+
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR|DST,E}},         {{
0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR|DST,E}},          {{
0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR|DST,E}},     {{
0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR|DST,E}},     {{
0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR|DST,E}},{{
0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR|DST,E}},{{
0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR|DST,E}},        {{
0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR|DST,E}},        {{
0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP,
 
   SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS|SRC|L_16|MEMRELAX,RD8,E}},  {{
0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}}EOP,
   SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{ABS|SRC|L_32|MEMRELAX,RD8,E }}, {{
0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }}EOP,
@@ -520,8 +520,8 @@
   NEW_SOP(O(O_OR,SL),0,6,"or.l"),{{IMM32,RD32,E
}},{{0x7,0xA,0x4,B30|RD32,IMM32LIST,E}} EOP,
   NEW_SOP(O(O_OR,SL),0,2,"or.l"),{{RS32,RD32,E
}},{{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E}} EOP,
 
-  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR,E}},{{
0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR,E}},{{
0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR|DST,E}},{{
0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR|DST,E}},{{
0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
 
   NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{{OR16,E,0}},{{
0x6,0xD,0x7,OR16,E,0,0,0,0}}EOP,
   NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{{OR32,E,0}},{{
PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}}EOP,
@@ -544,25 +544,25 @@
 
   SOP(O(O_SLEEP,SN),2,"sleep"),{{E,0,0}},{{ 0x0,0x1,0x8,0x0,E,0,0,0,0}}
EOP,
 
-  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR,RD8,E}},{{
0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
+  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR|SRC,RD8,E}},{{
0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
 
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RSIND,E}},
{{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
-
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B
31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B
30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RDDEC,E}},
{{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RSIND,E}},
{{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0
xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0
x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDDEC,E}},
{{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
 
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS16SRC,E}},
{{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS32SRC,E}},
{{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS16DST,E}},
{{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS32DST,E}},
{{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
 
-  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR,RD8,E}},{{
0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
+  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR|SRC,RD8,E}},{{
0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
 
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RSIND,E}},
{{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
-
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6
,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7
,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RDDEC,E}},
{{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RSIND,E}},
{{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1
,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+
NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1
,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDDEC,E}},
{{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
 
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS16SRC,E}},
{{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS32SRC,E}},
{{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS16DST,E}},
{{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS32DST,E}},
{{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
 
   SOP(O(O_SUB,SB),2,"sub.b"),{{RS8,RD8,E}},{{
0x1,0x8,RS8,RD8,E,0,0,0,0}}EOP,
 
@@ -585,8 +585,8 @@
   NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{{IMM32,RD32,E
}},{{0x7,0xA,0x5,B30|RD32,IMM32LIST,E}} EOP,
   NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{{RS32,RD32,E
}},{{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E}} EOP,
 
-  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR,E}},{{
0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR,E}},{{
0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR|DST,E}},{{
0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR|DST,E}},{{
0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
 
   NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}}
EOP,
 
NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B
30|RSINC,B30|RDINC,E}} EOP,
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