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Re: [RFA] More tweaks to arm_skip_prologue
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Michael Snyder <msnyder at redhat dot com>
- Cc: Richard dot Earnshaw at arm dot com, Michael Snyder <msnyder at cygnus dot com>, gdb-patches at sources dot redhat dot com, cagney at redhat dot com, rearnsha at arm dot com
- Date: Wed, 24 Apr 2002 10:15:26 +0100
- Subject: Re: [RFA] More tweaks to arm_skip_prologue
- Organization: ARM Ltd.
- Reply-to: Richard dot Earnshaw at arm dot com
> > If the sequence doesn't start with mov ip, sp then we either have a
> > scheduled prologue where the first instruction is messing with
> > call-clobbered register, or we have a frameless prologue. I suspect that
> > if are in this situation then we should use a different unwind function to
> > keep things simpler.
>
> You know way more about the architecture than I do, but
> check arm_scan_prologue -- it already does the same thing.
> I'd like to bring them into sync, and then think about
> possibly making them smarter.
>
I was thinking more along the lines of (in pseudo code)
arm_skip_prologue (...)
{
if (first_instruction == "mov ip, lr")
skip_atpcs_frame_prologue (...)
else
skip_prologue_maybe_frameless (...)
Maybe we could even make the sub-functions common to the two existing uses.
> > What about an "stmfd sp!, {...., lr}" (non-frame) prologue instruction.
>
> Can you give me a pattern to match for?
> I haven't actually seen that instruction in a prologue.
Try compiling the following with -O2 -fomit-frame-pointer.
void f (int *);
void h (int);
void g (int a, int b)
{
f(&a);
h(b);
}
You should get something like:
_g:
stmfd sp!, {r4, lr} @ Prologue
sub sp, sp, #4 @ Prologue
str r0, [sp, #0] @ Prologue
mov r4, r1 @ [note 1]
mov r0, sp
bl _f
mov r0, r4
bl _h
add sp, sp, #4
ldmfd sp!, {r4, pc}
[1] We should probably consider this instruction as part of the prologue
as well, but it isn't clear we can detect this reliably (ie not get any
false positives). It's possible that we could switch on any mov from
r0-r3.
R.