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Re: [RFA] Fix pending register stores in mips simulator
- To: Jim Blandy <jimb at cygnus dot com>
- Subject: Re: [RFA] Fix pending register stores in mips simulator
- From: Andrew Cagney <ac131313 at cygnus dot com>
- Date: Fri, 06 Apr 2001 12:10:38 -0400
- Cc: gdb-patches at sources dot redhat dot com
- References: <20010405032559.C594E5E9CB@zwingli.cygnus.com>
Jim Blandy wrote:
>
> Without this patch, the CFC1 and CTC1 instructions queue pending
> register stores off the end of the register array. In my test
> program, this ended up up zeroing elements in the CPU's register_width
> array. The sim refuse to provide the values of the registers whose
> widths are zero, which confuses GDB.
>
> 2001-04-04 Jim Blandy <jimb@redhat.com>
>
> * mips.igen (CFC1, CTC1): Pass the correct register numbers to
> PENDING_FILL. Use PENDING_SCHED directly to handle the pending
> set of the FCSR.
> * sim-main.h (COCIDX): Remove definition; this isn't supported by
> PENDING_FILL, and you can get the intended effect gracefully by
> calling PENDING_SCHED directly.
Yes, thansk.
Andrew
> Index: sim/mips/mips.igen
> ===================================================================
> RCS file: /cvs/cvsfiles/devo/sim/mips/mips.igen,v
> retrieving revision 1.86.72.1
> diff -c -r1.86.72.1 mips.igen
> *** sim/mips/mips.igen 2001/01/25 08:33:38 1.86.72.1
> --- sim/mips/mips.igen 2001/04/05 03:05:08
> ***************
> *** 2967,2977 ****
> if (X)
> {
> if (FS == 0)
> ! PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
> else if (FS == 31)
> ! PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
> /* else NOP */
> ! PENDING_FILL(COCIDX,0); /* special case */
> }
> else
> { /* control from */
> --- 2967,2977 ----
> if (X)
> {
> if (FS == 0)
> ! PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
> else if (FS == 31)
> ! PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
> /* else NOP */
> ! PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
> }
> else
> { /* control from */
> Index: sim/mips/sim-main.h
> ===================================================================
> RCS file: /cvs/cvsfiles/devo/sim/mips/sim-main.h,v
> retrieving revision 1.88.40.1
> diff -c -r1.88.40.1 sim-main.h
> *** sim/mips/sim-main.h 2001/01/25 08:33:39 1.88.40.1
> --- sim/mips/sim-main.h 2001/04/05 03:05:09
> ***************
> *** 404,410 ****
> #define Debug (REGISTERS[86])
> #define DEPC (REGISTERS[87])
> #define EPC (REGISTERS[88])
> - #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
>
> /* All internal state modified by signal_exception() that may need to be
> rolled back for passing moment-of-exception image back to gdb. */
> --- 404,409 ----