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[patch] sim/mips/mips.igen: make some insn encodings look more std.
- To: gdb-patches at sources dot redhat dot com
- Subject: [patch] sim/mips/mips.igen: make some insn encodings look more std.
- From: cgd at sibyte dot com (Chris G. Demetriou)
- Date: 05 Dec 2000 18:54:37 -0800
The following patch tweaks several of the instruction encodings to
make their instruction opcode fields more closely match the
instruction encodings as definted in the MIPS Instruction Set
Architecture documentation.
While this means no functional change, it can, for instance, be useful
for somebody perusing the source and the ISA documentation, since
e.g. it's obvious what the low 6 bit code for SPECIAL opcodes is.
Applies in sim/mips, over the top of my previous 2 patches.
2000-12-05 Chris Demetriou cgd@sibyte.com
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields so that they more closely match the MIPS ISA
documentation opcode partitioning.
I'm testing this together with the two patches I posted just previous
to this one:
http://sources.redhat.com/ml/gdb-patches/2000-12/msg00117.html
http://sources.redhat.com/ml/gdb-patches/2000-12/msg00116.html
using the mips64-elf and mipstx39-elf targets and the procedure
described in:
http://sources.redhat.com/ml/gdb/2000-12/msg00015.html
I'll post when those tests have finished.
cgd
=====
diff -rc ../src.P01/sim/mips/mips.igen ./sim/mips/mips.igen
*** ../src.P01/sim/mips/mips.igen Tue Dec 5 16:51:17 2000
--- ./sim/mips/mips.igen Tue Dec 5 16:58:30 2000
***************
*** 867,873 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
"ddiv r<RS>, r<RT>"
*mipsIII:
*mipsIV:
--- 867,873 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
"ddiv r<RS>, r<RT>"
*mipsIII:
*mipsIV:
***************
*** 942,948 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
*mipsI:
*mipsII:
--- 942,948 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
"div r<RS>, r<RT>"
*mipsI:
*mipsII:
***************
*** 978,984 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
*mipsI:
*mipsII:
--- 978,984 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
"divu r<RS>, r<RT>"
*mipsI:
*mipsII:
***************
*** 1058,1064 ****
do_dmultx (SD_, rs, rt, rd, 1);
}
! 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
*mipsIII:
*mipsIV:
--- 1058,1064 ----
do_dmultx (SD_, rs, rt, rd, 1);
}
! 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>"
*mipsIII:
*mipsIV:
***************
*** 1067,1073 ****
do_dmult (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>":RD == 0
"dmult r<RD>, r<RS>, r<RT>"
*vr5000:
--- 1067,1073 ----
do_dmult (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
"dmult r<RS>, r<RT>":RD == 0
"dmult r<RD>, r<RS>, r<RT>"
*vr5000:
***************
*** 1082,1088 ****
do_dmultx (SD_, rs, rt, rd, 0);
}
! 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
*mipsIII:
*mipsIV:
--- 1082,1088 ----
do_dmultx (SD_, rs, rt, rd, 0);
}
! 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
"dmultu r<RS>, r<RT>"
*mipsIII:
*mipsIV:
***************
*** 1091,1097 ****
do_dmultu (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
"dmultu r<RD>, r<RS>, r<RT>":RD == 0
"dmultu r<RS>, r<RT>"
*vr5000:
--- 1091,1097 ----
do_dmultu (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
"dmultu r<RD>, r<RS>, r<RT>":RD == 0
"dmultu r<RS>, r<RT>"
*vr5000:
***************
*** 1111,1117 ****
}
! 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
--- 1111,1117 ----
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
"dsll r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
***************
*** 1122,1128 ****
}
! 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
"dsll32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
--- 1122,1128 ----
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
"dsll32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
***************
*** 1133,1139 ****
GPR[RD] = GPR[RT] << s;
}
! 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
--- 1133,1139 ----
GPR[RD] = GPR[RT] << s;
}
! 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
"dsllv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
***************
*** 1149,1155 ****
}
! 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
--- 1149,1155 ----
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
"dsra r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
***************
*** 1160,1166 ****
}
! 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
"dsra32 r<RT>, r<RD>, <SHIFT>"
*mipsIII:
*mipsIV:
--- 1160,1166 ----
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
"dsra32 r<RT>, r<RD>, <SHIFT>"
*mipsIII:
*mipsIV:
***************
*** 1180,1186 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
"dsrav r<RT>, r<RD>, r<RS>"
*mipsIII:
*mipsIV:
--- 1180,1186 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
"dsrav r<RT>, r<RD>, r<RS>"
*mipsIII:
*mipsIV:
***************
*** 1196,1202 ****
}
! 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
--- 1196,1202 ----
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
"dsrl r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
***************
*** 1207,1213 ****
}
! 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
"dsrl32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
--- 1207,1213 ----
}
! 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
"dsrl32 r<RD>, r<RT>, <SHIFT>"
*mipsIII:
*mipsIV:
***************
*** 1227,1233 ****
! 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
"dsrlv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
--- 1227,1233 ----
! 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
"dsrlv r<RD>, r<RT>, r<RS>"
*mipsIII:
*mipsIV:
***************
*** 1238,1244 ****
}
! 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
"dsub r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
--- 1238,1244 ----
}
! 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
"dsub r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
***************
*** 1262,1268 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
--- 1262,1268 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
"dsubu r<RD>, r<RS>, r<RT>"
*mipsIII:
*mipsIV:
***************
*** 1307,1313 ****
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
! 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
*mipsI:
--- 1307,1313 ----
DELAY_SLOT (region | (INSTR_INDEX << 2));
}
! 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
"jalr r<RS>":RD == 31
"jalr r<RD>, r<RS>"
*mipsI:
***************
*** 1324,1330 ****
}
! 000000,5.RS,000000000000000001000:SPECIAL:32::JR
"jr r<RS>"
*mipsI:
*mipsII:
--- 1324,1330 ----
}
! 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
"jr r<RS>"
*mipsI:
*mipsII:
***************
*** 1759,1765 ****
! 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
--- 1759,1765 ----
! 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
***************
*** 1770,1776 ****
! 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
--- 1770,1776 ----
! 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
"movz r<RD>, r<RS>, r<RT>"
*mipsIV:
*vr5000:
***************
*** 1797,1803 ****
! 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsI:
*mipsII:
--- 1797,1803 ----
! 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsI:
*mipsII:
***************
*** 1827,1833 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
*mipsI:
*mipsII:
--- 1827,1833 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>"
*mipsI:
*mipsII:
***************
*** 1839,1845 ****
}
! 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":RD == 0
"mult r<RD>, r<RS>, r<RT>"
*vr5000:
--- 1839,1845 ----
}
! 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":RD == 0
"mult r<RD>, r<RS>, r<RT>"
*vr5000:
***************
*** 1863,1869 ****
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
*mipsI:
*mipsII:
--- 1863,1869 ----
TRACE_ALU_RESULT2 (HI, LO);
}
! 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>"
*mipsI:
*mipsII:
***************
*** 1874,1880 ****
do_multu (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":RD == 0
"multu r<RD>, r<RS>, r<RT>"
*vr5000:
--- 1874,1880 ----
do_multu (SD_, RS, RT, 0);
}
! 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":RD == 0
"multu r<RD>, r<RS>, r<RT>"
*vr5000:
***************
*** 2151,2157 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI:
--- 2151,2157 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
"nop":RD == 0 && RT == 0 && SHIFT == 0
"sll r<RD>, r<RT>, <SHIFT>"
*mipsI:
***************
*** 2176,2182 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
*mipsI:
*mipsII:
--- 2176,2182 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
"sllv r<RD>, r<RT>, r<RS>"
*mipsI:
*mipsII:
***************
*** 2197,2203 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
--- 2197,2203 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
"slt r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
***************
*** 2261,2267 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
--- 2261,2267 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
"sltu r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
***************
*** 2307,2313 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
*mipsI:
*mipsII:
--- 2307,2313 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
"srav r<RD>, r<RT>, r<RS>"
*mipsI:
*mipsII:
***************
*** 2353,2359 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
*mipsI:
*mipsII:
--- 2353,2359 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
"srlv r<RD>, r<RT>, r<RS>"
*mipsI:
*mipsII:
***************
*** 2367,2373 ****
}
! 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
--- 2367,2373 ----
}
! 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
"sub r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
***************
*** 2394,2400 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
--- 2394,2400 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
"subu r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
***************
*** 2532,2538 ****
}
! 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
"sync":STYPE == 0
"sync <STYPE>"
*mipsII:
--- 2532,2538 ----
}
! 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
"sync":STYPE == 0
"sync <STYPE>"
*mipsII:
***************
*** 2723,2729 ****
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
--- 2723,2729 ----
TRACE_ALU_RESULT (GPR[rd]);
}
! 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
"xor r<RD>, r<RS>, r<RT>"
*mipsI:
*mipsII:
***************
*** 3481,3487 ****
// MOVF
// MOVT
! 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
*vr5000:
--- 3481,3487 ----
// MOVF
// MOVT
! 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32::MOVtf
"mov%s<TF> r<RD>, r<RS>, <CC>"
*mipsIV:
*vr5000:
***************
*** 4056,4062 ****
}
! 010000,10000,000000000000000,111001:COP0:32::DI
"di"
*mipsI:
*mipsII:
--- 4056,4062 ----
}
! 010000,1,0000000000000000000,111001:COP0:32::DI
"di"
*mipsI:
*mipsII:
***************
*** 4066,4072 ****
*vr5000:
! 010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
*mipsIII:
*mipsIV:
--- 4066,4072 ----
*vr5000:
! 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
*mipsIII:
*mipsIV:
***************
*** 4075,4081 ****
}
! 010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
*mipsIII:
*mipsIV:
--- 4075,4081 ----
}
! 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
*mipsIII:
*mipsIV:
***************
*** 4084,4090 ****
}
! 010000,10000,000000000000000,111000:COP0:32::EI
"ei"
*mipsI:
*mipsII:
--- 4084,4090 ----
}
! 010000,1,0000000000000000000,111000:COP0:32::EI
"ei"
*mipsI:
*mipsII:
***************
*** 4094,4100 ****
*vr5000:
! 010000,10000,000000000000000,011000:COP0:32::ERET
"eret"
*mipsIII:
*mipsIV:
--- 4094,4100 ----
*vr5000:
! 010000,1,0000000000000000000,011000:COP0:32::ERET
"eret"
*mipsIII:
*mipsIV:
***************
*** 4145,4151 ****
}
! 010000,10000,000000000000000,010000:COP0:32::RFE
"rfe"
*mipsI:
*mipsII:
--- 4145,4151 ----
}
! 010000,1,0000000000000000000,010000:COP0:32::RFE
"rfe"
*mipsI:
*mipsII:
***************
*** 4173,4179 ****
! 010000,10000,000000000000000,001000:COP0:32::TLBP
"tlbp"
*mipsI:
*mipsII:
--- 4173,4179 ----
! 010000,1,0000000000000000000,001000:COP0:32::TLBP
"tlbp"
*mipsI:
*mipsII:
***************
*** 4183,4189 ****
*vr5000:
! 010000,10000,000000000000000,000001:COP0:32::TLBR
"tlbr"
*mipsI:
*mipsII:
--- 4183,4189 ----
*vr5000:
! 010000,1,0000000000000000000,000001:COP0:32::TLBR
"tlbr"
*mipsI:
*mipsII:
***************
*** 4193,4199 ****
*vr5000:
! 010000,10000,000000000000000,000010:COP0:32::TLBWI
"tlbwi"
*mipsI:
*mipsII:
--- 4193,4199 ----
*vr5000:
! 010000,1,0000000000000000000,000010:COP0:32::TLBWI
"tlbwi"
*mipsI:
*mipsII:
***************
*** 4203,4209 ****
*vr5000:
! 010000,10000,000000000000000,000110:COP0:32::TLBWR
"tlbwr"
*mipsI:
*mipsII:
--- 4203,4209 ----
*vr5000:
! 010000,1,0000000000000000000,000110:COP0:32::TLBWR
"tlbwr"
*mipsI:
*mipsII: