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[patch] move GDB_TARGET_IS_MIPS64 to mips-tdep.c
- To: GDB Patches <gdb-patches at sourceware dot cygnus dot com>
- Subject: [patch] move GDB_TARGET_IS_MIPS64 to mips-tdep.c
- From: Andrew Cagney <ac131313 at cygnus dot com>
- Date: Mon, 12 Jun 2000 14:36:10 +1000
- Organization: Cygnus Solutions
FYI,
Andrew
Mon Jun 12 14:26:02 2000 Andrew Cagney <cagney@b1.cygnus.com>
* mips-tdep.c (GDB_TARGET_IS_MIPS64): Define.
(struct gdbarch_tdep): Add gdb_target_is_mips64.
(mips_addr_bits_remove): Update.
(mips_gdbarch_init): Initialize.
* config/mips/tm-mips64.h (GDB_TARGET_IS_MIPS64,
GDB_TARGET_IS_MIPS64): Delete.
Index: mips-tdep.c
===================================================================
RCS file: /cvs/src/src/gdb/mips-tdep.c,v
retrieving revision 1.15
diff -p -r1.15 mips-tdep.c
*** mips-tdep.c 2000/06/10 05:37:47 1.15
--- mips-tdep.c 2000/06/12 04:29:55
*************** struct gdbarch_tdep
*** 122,127 ****
--- 122,128 ----
int mips_fp_register_double;
int mips_regs_have_home_p;
int mips_default_stack_argsize;
+ int gdb_target_is_mips64;
};
#if GDB_MULTI_ARCH
*************** mips_stack_argsize (void)
*** 215,221 ****
return 4;
}
!
#define VM_MIN_ADDRESS (CORE_ADDR)0x400000
--- 216,224 ----
return 4;
}
! #if GDB_MULTI_ARCH
! #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
! #endif
#define VM_MIN_ADDRESS (CORE_ADDR)0x400000
*************** CORE_ADDR
*** 1308,1338 ****
mips_addr_bits_remove (addr)
CORE_ADDR addr;
{
! #if GDB_TARGET_IS_MIPS64
! if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff))
{
! /* This hack is a work-around for existing boards using PMON,
! the simulator, and any other 64-bit targets that doesn't have
! true 64-bit addressing. On these targets, the upper 32 bits
! of addresses are ignored by the hardware. Thus, the PC or SP
! are likely to have been sign extended to all 1s by instruction
! sequences that load 32-bit addresses. For example, a typical
! piece of code that loads an address is this:
! lui $r2, <upper 16 bits>
! ori $r2, <lower 16 bits>
! But the lui sign-extends the value such that the upper 32 bits
! may be all 1s. The workaround is simply to mask off these bits.
! In the future, gcc may be changed to support true 64-bit
! addressing, and this masking will have to be disabled. */
addr &= (CORE_ADDR) 0xffffffff;
}
- #else
- /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
- BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
- So we still have to mask off useless bits from addresses. */
- addr &= (CORE_ADDR) 0xffffffff;
- #endif
-
return addr;
}
--- 1311,1344 ----
mips_addr_bits_remove (addr)
CORE_ADDR addr;
{
! if (GDB_TARGET_IS_MIPS64)
! {
! if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff))
! {
! /* This hack is a work-around for existing boards using
! PMON, the simulator, and any other 64-bit targets that
! doesn't have true 64-bit addressing. On these targets,
! the upper 32 bits of addresses are ignored by the
! hardware. Thus, the PC or SP are likely to have been
! sign extended to all 1s by instruction sequences that
! load 32-bit addresses. For example, a typical piece of
! code that loads an address is this: lui $r2, <upper 16
! bits> ori $r2, <lower 16 bits> But the lui sign-extends
! the value such that the upper 32 bits may be all 1s. The
! workaround is simply to mask off these bits. In the
! future, gcc may be changed to support true 64-bit
! addressing, and this masking will have to be disabled. */
! addr &= (CORE_ADDR) 0xffffffff;
! }
! }
! else
{
! /* Even when GDB is configured for some 32-bit targets
! (e.g. mips-elf), BFD is configured to handle 64-bit targets,
! so CORE_ADDR is 64 bits. So we still have to mask off
! useless bits from addresses. */
addr &= (CORE_ADDR) 0xffffffff;
}
return addr;
}
*************** mips_gdbarch_init (info, arches)
*** 3942,3947 ****
--- 3948,3954 ----
tdep->mips_last_arg_regnum = ZERO_REGNUM + 7;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15;
tdep->mips_regs_have_home_p = 1;
+ tdep->gdb_target_is_mips64 = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
*************** mips_gdbarch_init (info, arches)
*** 3953,3958 ****
--- 3960,3966 ----
tdep->mips_last_arg_regnum = ZERO_REGNUM + 7;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15;
tdep->mips_regs_have_home_p = 1;
+ tdep->gdb_target_is_mips64 = 1;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
*************** mips_gdbarch_init (info, arches)
*** 3964,3969 ****
--- 3972,3978 ----
tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 0;
+ tdep->gdb_target_is_mips64 = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
*************** mips_gdbarch_init (info, arches)
*** 3975,3980 ****
--- 3984,3990 ----
tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 0;
+ tdep->gdb_target_is_mips64 = 1;
set_gdbarch_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
set_gdbarch_long_long_bit (gdbarch, 64);
*************** mips_gdbarch_init (info, arches)
*** 3986,3991 ****
--- 3996,4002 ----
tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 0;
+ tdep->gdb_target_is_mips64 = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
*************** mips_gdbarch_init (info, arches)
*** 3997,4002 ****
--- 4008,4014 ----
tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
tdep->mips_regs_have_home_p = 1;
+ tdep->gdb_target_is_mips64 = 0;
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
Index: config/mips/tm-mips.h
===================================================================
RCS file: /cvs/src/src/gdb/config/mips/tm-mips.h,v
retrieving revision 1.12
diff -p -r1.12 tm-mips.h
*** tm-mips.h 2000/06/08 06:35:40 1.12
--- tm-mips.h 2000/06/12 04:29:57
*************** struct value;
*** 35,44 ****
#include "coff/sym.h" /* Needed for PDR below. */
#include "coff/symconst.h"
- #if !defined (GDB_TARGET_IS_MIPS64)
- #define GDB_TARGET_IS_MIPS64 0
- #endif
-
#if !defined (MIPS_EABI)
#define MIPS_EABI 0
#endif
--- 35,40 ----
Index: config/mips/tm-mips64.h
===================================================================
RCS file: /cvs/src/src/gdb/config/mips/tm-mips64.h,v
retrieving revision 1.2
diff -p -r1.2 tm-mips64.h
*** tm-mips64.h 2000/06/08 06:35:40 1.2
--- tm-mips64.h 2000/06/12 04:29:57
***************
*** 1,5 ****
/* Target machine parameters for MIPS r4000
! Copyright 1994, 1996 Free Software Foundation, Inc.
Contributed by Ian Lance Taylor (ian@cygnus.com)
This file is part of GDB.
--- 1,5 ----
/* Target machine parameters for MIPS r4000
! Copyright 1994, 1996, 2000 Free Software Foundation, Inc.
Contributed by Ian Lance Taylor (ian@cygnus.com)
This file is part of GDB.
***************
*** 18,25 ****
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-
- #define GDB_TARGET_IS_MIPS64 1
/* Use eight byte registers. */
#define MIPS_REGSIZE 8
--- 18,23 ----