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[patch] sim/h8300/compile.c
- To: gdb-patches at sourceware dot cygnus dot com
- Subject: [patch] sim/h8300/compile.c
- From: Kazu Hirata <kazu at hxi dot com>
Hi,
I separated patch for binutils and gdb.
Attached is a patch for sim/h8300/compile.c. The patch fixes a bug
that simulator does not distinguish adds/subs and inc/dec.[wl] correctly.
In sim/h8300/compile.c, "if (looking_for & DBIT)" is to accept
inc/dec.[wl]. It must reject adds/subs because it is taken care of by
"if (looking_for & KBIT)". The detailed reasoning is given in:
http://sourceware.cygnus.com/ml/binutils/2000-06/msg00111.html
Now, "if (looking_for & KBIT)" is to accept adds and subs, but must
reject inc/dec.[wl] because they are taken care of by "if (looking_for
& DBIT)". Therefore, "goto fail" must be the default case of the
switch statement "if (looking_for & KBIT)".
By the way, the patch includes a lot of formatting changes. That is
because I think it's good to make the following two functions look
similar.
bfd_h8_disassemble () in opcodes/h8300-dis.c
decode () in sim/h8300/compile.c
One is a disassembler; the other is a simulator. Thus, the opcode
interpretation part should be identical. Right now, taking a diff
between the two functions gives lots of white-space differences, which
are meaningless. So, if you could, please apply the patch as it is.
Thanks,
Kazu Hirata
===File ~/h8300-hms/gdb/ChangeLog-compile===================
2000-06-07 Kazu Hirata <kazu@hxi.com>
* compile.c: Fix formatting.
(decode): Distinguish adds/subs, inc/dec.[wl] correctly.
============================================================
===File ~/h8300-hms/gdb/compile.patch=======================
Index: sim/h8300/compile.c
===================================================================
RCS file: /cvs/src/src/sim/h8300/compile.c,v
retrieving revision 1.1.1.2
diff -u -r1.1.1.2 compile.c
--- compile.c 1999/04/26 18:32:21 1.1.1.2
+++ compile.c 2000/06/07 17:56:17
@@ -109,7 +109,6 @@
static int memory_size;
-
static int
get_now ()
{
@@ -125,7 +124,6 @@
return 1;
}
-
static int
bitfrom (x)
{
@@ -142,8 +140,7 @@
}
}
-static
-unsigned int
+static unsigned int
lvalue (x, rn)
{
switch (x / 4)
@@ -156,8 +153,8 @@
return X (OP_REG, SP);
case OP_MEM:
-
return X (OP_MEM, SP);
+
default:
abort ();
}
@@ -181,7 +178,7 @@
int size = 0;
dst->dst.type = -1;
dst->src.type = -1;
- /* Find the exact opcode/arg combo */
+ /* Find the exact opcode/arg combo. */
while (q->name)
{
op_type *nib;
@@ -207,40 +204,40 @@
{
if (!(((int) thisnib & 0x8) != 0))
goto fail;
- looking_for = (op_type) ((int) looking_for & ~(int)
- B31);
+
+ looking_for = (op_type) ((int) looking_for & ~(int) B31);
thisnib &= 0x7;
}
+
if ((int) looking_for & (int) B30)
{
if (!(((int) thisnib & 0x8) == 0))
goto fail;
+
looking_for = (op_type) ((int) looking_for & ~(int) B30);
}
+
if (looking_for & DBIT)
{
- if ((looking_for & 5) != (thisnib & 5))
+ /* Exclude adds/subs by looking at bit 0 and 2, and
+ make sure the operand size, either w or l,
+ matches by looking at bit 1. */
+ if ((looking_for & 7) != (thisnib & 7))
goto fail;
+
abs = (thisnib & 0x8) ? 2 : 1;
}
else if (looking_for & (REG | IND | INC | DEC))
{
if (looking_for & REG)
{
- /*
- * Can work out size from the
- * register
- */
+ /* Can work out size from the register. */
size = bitfrom (looking_for);
}
if (looking_for & SRC)
- {
- rs = thisnib;
- }
+ rs = thisnib;
else
- {
- rd = thisnib;
- }
+ rd = thisnib;
}
else if (looking_for & L_16)
{
@@ -253,10 +250,7 @@
}
else if (looking_for & ABSJMP)
{
- abs =
- (data[1] << 16)
- | (data[2] << 8)
- | (data[3]);
+ abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
}
else if (looking_for & MEMIND)
{
@@ -265,6 +259,7 @@
else if (looking_for & L_32)
{
int i = len >> 1;
+
abs = (data[i] << 24)
| (data[i + 1] << 16)
| (data[i + 2] << 8)
@@ -275,12 +270,13 @@
else if (looking_for & L_24)
{
int i = len >> 1;
+
abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
plen = 24;
}
else if (looking_for & IGNORE)
{
- /* nothing to do */
+ ;
}
else if (looking_for & DISPREG)
{
@@ -299,6 +295,8 @@
case 0:
abs = 1;
break;
+ default:
+ goto fail;
}
}
else if (looking_for & L_8)
@@ -313,9 +311,9 @@
{
plen = 8;
abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
- abs |= data[len >> 1] & 0xff ;
+ abs |= data[len >> 1] & 0xff;
}
- else
+ else
{
abs = data[len >> 1] & 0xff;
}
@@ -330,7 +328,7 @@
{
dst->op = q;
- /* Fill in the args */
+ /* Fill in the args. */
{
op_type *args = q->args.nib;
int hadone = 0;
@@ -342,15 +340,11 @@
ea_type *p;
if (x & DST)
- {
- p = &(dst->dst);
- }
+ p = &(dst->dst);
else
- {
- p = &(dst->src);
- }
+ p = &(dst->src);
- if (x & (L_3))
+ if (x & L_3)
{
p->type = X (OP_IMM, size);
p->literal = bit;
@@ -362,8 +356,8 @@
}
else if (x & REG)
{
- /* Reset the size, some
- ops (like mul) have two sizes */
+ /* Reset the size, some ops (like mul)
+ have two sizes. */
size = bitfrom (x);
p->type = X (OP_REG, size);
@@ -425,12 +419,9 @@
}
}
- /*
- * But a jmp or a jsr gets
- * automagically lvalued, since we
- * branch to their address not their
- * contents
- */
+ /* But a jmp or a jsr gets automagically lvalued,
+ since we branch to their address not their
+ contents. */
if (q->how == O (O_JSR, SB)
|| q->how == O (O_JMP, SB))
{
@@ -457,9 +448,7 @@
return;
}
else
- {
- printf ("Dont understand %x \n", looking_for);
- }
+ printf ("Dont understand %x \n", looking_for);
}
len++;
@@ -470,10 +459,10 @@
q++;
}
+ /* Fell off the end. */
dst->opcode = O (O_ILL, SB);
}
-
static void
compile (pc)
{
@@ -627,9 +616,7 @@
}
}
-
-static
-void
+static void
store (arg, n)
ea_type *arg;
int n;
@@ -655,8 +642,8 @@
t &= cpu.mask;
SET_L_REG (rn, t);
SET_MEMORY_B (t, n);
-
break;
+
case X (OP_DEC, SW):
t = (GET_L_REG (rn) - 2) & cpu.mask;
SET_L_REG (rn, t);
@@ -705,8 +692,7 @@
littleendian;
-static
-void
+static void
init_pointers ()
{
static int init;
@@ -1810,7 +1796,7 @@
#define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
#define FP_REGNUM R6_REGNUM /* Contains address of executing
- * stack frame */
+ * stack frame */
#define CCR_REGNUM 8 /* Contains processor status */
#define PC_REGNUM 9 /* Contains program counter */
============================================================