This is the mail archive of the
gdb-cvs@sourceware.org
mailing list for the GDB project.
[binutils-gdb/gdb-7.12-branch] Keep reserved bits in CPSR on write
- From: Yao Qi <qiyao at sourceware dot org>
- To: gdb-cvs at sourceware dot org
- Date: 21 Sep 2016 11:49:10 -0000
- Subject: [binutils-gdb/gdb-7.12-branch] Keep reserved bits in CPSR on write
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=61f97a2f940e36d4b4c87ef5b28a49e6834f8e68
commit 61f97a2f940e36d4b4c87ef5b28a49e6834f8e68
Author: Yao Qi <yao.qi@linaro.org>
Date: Fri Sep 16 14:58:31 2016 +0100
Keep reserved bits in CPSR on write
In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html
I cleared reserved bits when reading CPSR. It makes a problem that
these bits (zero) are written back to kernel through ptrace, and it
changes the state of the processor on some recent kernel, which is
unexpected.
In this patch, I keep these reserved bits when write CPSR back to
hardware.
gdb:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
bits 20 to 23.
gdb/gdbserver:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to
23.
Diff:
---
gdb/ChangeLog | 5 +++++
gdb/aarch32-linux-nat.c | 11 +++++++++--
gdb/gdbserver/ChangeLog | 5 +++++
gdb/gdbserver/linux-aarch32-low.c | 4 ++++
4 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 6f45d50..63359d4 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2016-09-21 Yao Qi <yao.qi@linaro.org>
+
+ * aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
+ bits 20 to 23.
+
2016-09-20 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
* rs6000-tdep.c (ppc_process_record_op31): Fix record of Store String
diff --git a/gdb/aarch32-linux-nat.c b/gdb/aarch32-linux-nat.c
index 72bf644..2df672d 100644
--- a/gdb/aarch32-linux-nat.c
+++ b/gdb/aarch32-linux-nat.c
@@ -67,8 +67,15 @@ aarch32_gp_regcache_collect (const struct regcache *regcache, uint32_t *regs,
if (arm_apcs_32
&& REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM))
- regcache_raw_collect (regcache, ARM_PS_REGNUM,
- ®s[ARM_CPSR_GREGNUM]);
+ {
+ uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
+
+ regcache_raw_collect (regcache, ARM_PS_REGNUM,
+ ®s[ARM_CPSR_GREGNUM]);
+ /* Keep reserved bits bit 20 to bit 23. */
+ regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff)
+ | (cpsr & 0x00f00000));
+ }
}
/* Supply VFP registers contents, stored in REGS, to REGCACHE.
diff --git a/gdb/gdbserver/ChangeLog b/gdb/gdbserver/ChangeLog
index a2031bf..e2c43a7 100644
--- a/gdb/gdbserver/ChangeLog
+++ b/gdb/gdbserver/ChangeLog
@@ -1,3 +1,8 @@
+2016-09-21 Yao Qi <yao.qi@linaro.org>
+
+ * linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to
+ 23.
+
2016-08-31 Antoine Tremblay <antoine.tremblay@ericsson.com>
* linux-low.c (linux_wait_1): Move event switch after unsuspend_lwps.
diff --git a/gdb/gdbserver/linux-aarch32-low.c b/gdb/gdbserver/linux-aarch32-low.c
index e6971d5..463bce6 100644
--- a/gdb/gdbserver/linux-aarch32-low.c
+++ b/gdb/gdbserver/linux-aarch32-low.c
@@ -62,11 +62,15 @@ arm_fill_gregset (struct regcache *regcache, void *buf)
{
int i;
uint32_t *regs = (uint32_t *) buf;
+ uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++)
collect_register (regcache, i, ®s[i]);
collect_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]);
+ /* Keep reserved bits bit 20 to bit 23. */
+ regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff)
+ | (cpsr & 0x00f00000));
}
/* Supply GP registers contents, stored in BUF, to REGCACHE. */