src/sim/rx ChangeLog config.in configure confi ...

[dj at sourceware dot org]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	dj@sourceware.org	2010-07-28 21:58:22

Modified files:
	sim/rx         : ChangeLog config.in configure configure.in 
	                 cpu.h main.c mem.c mem.h reg.c rx.c trace.c 
Added files:
	sim/rx         : README.txt 

Log message:
	[sim/rx]
	* README.txt: New.
	* config.h (CYCLE_ACCURATE, CYCLE_STATS): New.
	* configure.in (--enable-cycle-accurate, --enable-cycle-stats):
	New.  Default to enabled.
	* configure: Regenerate.
	
	* cpu.h (regs_type): Add cycle tracking info.
	(reset_pipeline_stats): Declare.
	(halt_pipeline_stats): Declare.
	(pipeline_stats): Declare.
	* main.c (done): Call pipeline_stats().
	* mem.h (rx_mem_ptr): Moved to here ...
	* mem.c (mem_ptr): ... from here.  Rename throughout.
	(mem_put_byte): Move LEDs to Port A.  Add Port B to control cycle
	statistics.  Move UART to SCI4.
	(mem_put_hi): Add TPU 1-2.  TPU 1 and 2 count CPU cycles.
	* reg.c (init_regs): Set Rt reg to -1 (no reg).
	* rx.c: Add cycle counting and statistics throughout.
	(rx_get_byte): Optimize for speed.
	(decode_opcode): Likewise.
	(reset_pipeline_stats): New.
	(halt_pipeline_stats): New.
	(pipeline_stats): New.
	* trace.c (sim_disasm_one): Print cycle count.
	
	[include/opcode]
	* rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/README.txt.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/ChangeLog.diff?cvsroot=src&r1=1.9&r2=1.10
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/config.in.diff?cvsroot=src&r1=1.2&r2=1.3
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/configure.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/configure.in.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/cpu.h.diff?cvsroot=src&r1=1.2&r2=1.3
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/main.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/mem.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/mem.h.diff?cvsroot=src&r1=1.2&r2=1.3
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/reg.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/rx.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/rx/trace.c.diff?cvsroot=src&r1=1.2&r2=1.3